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reg 2,128 would disable IO devices (including keyboard, mouse and sdc…
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…ard) which caused incompatibility with applications which use this to disable the ESP Wifi card (e.g. to reduce noise on the audio output).
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@mdovey
mdovey committed Mar 16, 2022
1 parent dbe455a commit af28c09
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40 changes: 32 additions & 8 deletions ip/pmod_esp32/component.xml
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Expand Up @@ -316,7 +316,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>75a694cb</spirit:value>
<spirit:value>80fab65e</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand All @@ -332,7 +332,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>75a694cb</spirit:value>
<spirit:value>80fab65e</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand Down Expand Up @@ -693,6 +693,19 @@
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>enable</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>gpio0_i</spirit:name>
<spirit:wire>
Expand Down Expand Up @@ -824,7 +837,7 @@
<spirit:file>
<spirit:name>../../srcs/sources/new/pmod/pmod_esp32.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_1045934b</spirit:userFileType>
<spirit:userFileType>CHECKSUM_123644bb</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
Expand Down Expand Up @@ -890,11 +903,11 @@
</xilinx:taxonomies>
<xilinx:displayName>pmod_esp32_v1_1</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:coreRevision>3</xilinx:coreRevision>
<xilinx:coreRevision>4</xilinx:coreRevision>
<xilinx:upgrades>
<xilinx:canUpgradeFrom>specnext.com:specnext:pmod_esp32:1.0</xilinx:canUpgradeFrom>
</xilinx:upgrades>
<xilinx:coreCreationDateTime>2021-12-30T11:18:16Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2022-03-15T13:06:19Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="ui.data.coregen.df@63c72f66_ARCHIVE_LOCATION">v:/ip/pmod_esp32</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@48fc63ff_ARCHIVE_LOCATION">v:/ip/pmod_esp32</xilinx:tag>
Expand Down Expand Up @@ -930,13 +943,24 @@
<xilinx:tag xilinx:name="ui.data.coregen.df@63c1dafc_ARCHIVE_LOCATION">v:/ip/pmod_esp32</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@68d434d3_ARCHIVE_LOCATION">v:/ip/pmod_esp32</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@632cb70f_ARCHIVE_LOCATION">v:/ip/pmod_esp32</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@4ceedf19_ARCHIVE_LOCATION">v:/ip/pmod_esp32</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@2c31a6bb_ARCHIVE_LOCATION">v:/ip/pmod_esp32</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@56ba5e1c_ARCHIVE_LOCATION">v:/ip/pmod_esp32</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@376a962f_ARCHIVE_LOCATION">v:/ip/pmod_esp32</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@1f9bc089_ARCHIVE_LOCATION">v:/ip/pmod_esp32</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@19026b0d_ARCHIVE_LOCATION">v:/ip/pmod_esp32</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@185d7888_ARCHIVE_LOCATION">v:/ip/pmod_esp32</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.df@6c3b7272_ARCHIVE_LOCATION">v:/ip/pmod_esp32</xilinx:tag>
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</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2021.2</xilinx:xilinxVersion>
<xilinx:xilinxVersion>2021.2.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="bfe57910"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="be1e31ba"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="a3bcf783"/>
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<xilinx:checksum xilinx:scope="ports" xilinx:value="d214ef5b"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="440e390e"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
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4 changes: 3 additions & 1 deletion ip/pmod_esp32/src/pmod_esp32.v
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Original file line number Diff line number Diff line change
Expand Up @@ -76,6 +76,8 @@ module pmod_esp32(
output uart_rx,
input uart_tx,

input enable,

(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 gpio0 TRI_I" *)
(* X_INTERFACE_MODE = "mirroredMaster" *)
output gpio0_i,
Expand Down Expand Up @@ -115,7 +117,7 @@ module pmod_esp32(
assign pin7_o = gpio2_o;
assign pin7_t = gpio2_t;

assign pin8_o = 1'b1;
assign pin8_o = enable;
assign pin8_t = 1'b0;

assign pin9_o = 1'b0;
Expand Down
79 changes: 53 additions & 26 deletions ip/zxaudio/component.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -69,29 +69,29 @@
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>reset</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:name>clk_peripheral</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>reset</spirit:name>
<spirit:name>clk_peripheral</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.RESET.POLARITY">ACTIVE_HIGH</spirit:value>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK_PERIPHERAL.ASSOCIATED_RESET">reset</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>clk_peripheral</spirit:name>
<spirit:name>clk_22m59</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
Expand All @@ -101,36 +101,36 @@
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>clk_peripheral</spirit:name>
<spirit:name>clk_22m59</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK_PERIPHERAL.ASSOCIATED_RESET">reset</spirit:value>
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK_22M59.ASSOCIATED_RESET"/>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>clk_22m59</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:name>resetn</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>clk_22m59</spirit:name>
<spirit:name>resetn</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK_22M59.ASSOCIATED_RESET"/>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.RESETN.POLARITY" spirit:choiceRef="choice_list_74b5137e">ACTIVE_LOW</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
Expand All @@ -152,7 +152,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>9949669f</spirit:value>
<spirit:value>0771f63d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand All @@ -171,7 +171,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>b1abdf70</spirit:value>
<spirit:value>1f3661c3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand Down Expand Up @@ -440,7 +440,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>reset</spirit:name>
<spirit:name>resetn</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
Expand Down Expand Up @@ -504,6 +504,11 @@
</spirit:modelParameters>
</spirit:model>
<spirit:choices>
<spirit:choice>
<spirit:name>choice_list_74b5137e</spirit:name>
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
<spirit:choice>
<spirit:name>choice_pairs_de212931</spirit:name>
<spirit:enumeration spirit:text="Audio">0</spirit:enumeration>
Expand Down Expand Up @@ -755,7 +760,7 @@
<spirit:file>
<spirit:name>../../srcs/sources/new/audio/audio_wrapper.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_208ba4b7</spirit:userFileType>
<spirit:userFileType>CHECKSUM_ffbee688</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
Expand Down Expand Up @@ -1053,11 +1058,11 @@
</xilinx:taxonomies>
<xilinx:displayName>zxaudio_v2_5</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:coreRevision>80</xilinx:coreRevision>
<xilinx:coreRevision>82</xilinx:coreRevision>
<xilinx:upgrades>
<xilinx:canUpgradeFrom>specnext.com:specnext:audio_wrapper:1.0</xilinx:canUpgradeFrom>
</xilinx:upgrades>
<xilinx:coreCreationDateTime>2022-02-21T19:58:19Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2022-03-15T12:59:25Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="ui.data.coregen.df@2adc191f_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@272f3c7_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
Expand Down Expand Up @@ -2036,13 +2041,35 @@
<xilinx:tag xilinx:name="ui.data.coregen.df@c5c127a_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@8f3ae5d_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@7fdd3047_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@339cf475_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@54dc7484_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@2b73df6a_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@aa4289e_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@7dea2c30_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@7227ebc4_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@532095f6_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@626f65ea_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@6b001c7a_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@915c13f_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@77c375a4_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@629b6184_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@56608cef_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@80e8a82_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@5b869f1e_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@2083c4a6_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@4a642d61_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@1f508b6d_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@3cdb65fd_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.df@2586d15e_ARCHIVE_LOCATION">v:/ip/zxaudio</xilinx:tag>
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<xilinx:packagingInfo>
<xilinx:xilinxVersion>2021.2.1</xilinx:xilinxVersion>
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<xilinx:checksum xilinx:scope="parameters" xilinx:value="4fc771c2"/>
</xilinx:packagingInfo>
Expand Down
12 changes: 6 additions & 6 deletions ip/zxaudio/sim/audio.v
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2021.2.1 (win64) Build 3414424 Sun Dec 19 10:57:22 MST 2021
//Date : Thu Feb 17 19:44:02 2022
//Date : Tue Mar 15 12:51:10 2022
//Host : AW13R3 running 64-bit major release (build 9200)
//Command : generate_target audio.bd
//Design : audio
Expand All @@ -26,7 +26,7 @@ module audio
lineout_sclk,
lineout_sdout,
psg_en,
reset,
resetn,
tape_ear,
tape_mic,
tape_pwm);
Expand All @@ -45,7 +45,7 @@ module audio
output lineout_sclk;
output lineout_sdout;
output psg_en;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.RESET RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH" *) input reset;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.RESETN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.RESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input resetn;
output tape_ear;
input tape_mic;
output tape_pwm;
Expand Down Expand Up @@ -74,7 +74,7 @@ module audio
wire clk_peripheral_1;
wire debounce_0_button_o;
wire linein_sdin_1;
wire reset_1;
wire resetn_1;
wire sigma_delta_dac_0_DACout;
wire sigma_delta_dac_1_DACout;
wire tape_ear_0_ear;
Expand All @@ -97,7 +97,7 @@ module audio
assign lineout_sclk = axis_i2s2_0_tx_sclk;
assign lineout_sdout = axis_i2s2_0_tx_sdout;
assign psg_en = audio_psg_0_psg_en;
assign reset_1 = reset;
assign resetn_1 = resetn;
assign tape_ear = debounce_0_button_o;
assign tape_mic_1 = tape_mic;
assign tape_pwm = sigma_delta_dac_1_DACout;
Expand All @@ -121,7 +121,7 @@ module audio
.psg_en(audio_psg_0_psg_en));
audio_audio_reset_0_0 audio_reset_0
(.clk(clk_22m59),
.reset(reset_1),
.resetn(resetn_1),
.rst(audio_reset_0_rst),
.rstn(audio_reset_0_rstn));
audio_axis_i2s2_0_0 axis_i2s2_0
Expand Down
10 changes: 5 additions & 5 deletions ip/zxaudio/sim/audio_audio_reset_0_0.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -55,15 +55,15 @@
(* IP_DEFINITION_SOURCE = "module_ref" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module audio_audio_reset_0_0 (
reset,
resetn,
rst,
rstn,
clk
);

(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset RST" *)
input wire reset;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME resetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 resetn RST" *)
input wire resetn;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME rst, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 rst RST" *)
output wire rst;
Expand All @@ -75,7 +75,7 @@ output wire rstn;
input wire clk;

audio_reset inst (
.reset(reset),
.resetn(resetn),
.rst(rst),
.rstn(rstn),
.clk(clk)
Expand Down
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