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Update (2024.07.01)
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34304: 8333722: Fix CompilerDirectives for non-compiler JVM variants
33726: Link time optimization breaks build: no match insn: amcas_db_d $r12,$r25,$r15
33624: Reconstruct the StrComp agenda
34183: nmethod entry barrier is missing in LoongArch64TestAssembler.java
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@loongson-jvm
loongson-jvm authored Jul 1, 2024
1 parent aca0f3a commit 1fe76a3
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Showing 10 changed files with 816 additions and 511 deletions.
806 changes: 512 additions & 294 deletions src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.cpp
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24 changes: 20 additions & 4 deletions src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -44,10 +44,26 @@
Register tmp1, Register tmp2, Register tmp3);

// Compare strings.
void string_compare(Register str1, Register str2,
Register cnt1, Register cnt2, Register result,
int ae, Register tmp1, Register tmp2,
FloatRegister vtmp1, FloatRegister vtmp2);
void string_compareL(Register str1, Register str2,
Register cnt1, Register cnt2,
Register result,
Register tmp1, Register tmp2,
FloatRegister vtmp1, FloatRegister vtmp2);
void string_compareU(Register str1, Register str2,
Register cnt1, Register cnt2,
Register result,
Register tmp1, Register tmp2,
FloatRegister vtmp1, FloatRegister vtmp2);
void string_compareLU(Register str1, Register str2,
Register cnt1, Register cnt2,
Register result,
Register tmp1, Register tmp2,
FloatRegister vtmp1, FloatRegister vtmp2);
void string_compareUL(Register str1, Register str2,
Register cnt1, Register cnt2,
Register result,
Register tmp1, Register tmp2,
FloatRegister vtmp1, FloatRegister vtmp2);

// Find index of char in Latin-1 string
void stringL_indexof_char(Register str1, Register cnt1,
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4 changes: 2 additions & 2 deletions src/hotspot/cpu/loongarch/jvmciCodeInstaller_loongarch.cpp
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2022, 2023, Loongson Technology. All rights reserved.
* Copyright (c) 2022, 2024, Loongson Technology. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -92,7 +92,7 @@ void CodeInstaller::pd_patch_MetaspaceConstant(int pc_offset, HotSpotCompiledCod
void CodeInstaller::pd_patch_DataSectionReference(int pc_offset, int data_offset, JVMCI_TRAPS) {
address pc = _instructions->start() + pc_offset;
NativeInstruction* inst = nativeInstruction_at(pc);
if (inst->is_pcaddu12i_add()) {
if (inst->is_pcaddi()) {
address dest = _constants->start() + data_offset;
_instructions->relocate(pc, section_word_Relocation::spec((address) dest, CodeBuffer::SECT_CONSTS));
JVMCI_event_3("relocating at " PTR_FORMAT " (+%d) with destination at %d", p2i(pc), pc_offset, data_offset);
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103 changes: 75 additions & 28 deletions src/hotspot/cpu/loongarch/loongarch_64.ad
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Original file line number Diff line number Diff line change
Expand Up @@ -3230,6 +3230,15 @@ operand mA2RegI() %{
interface(REG_INTER);
%}

operand mA4RegI() %{
constraint(ALLOC_IN_RC(a4_reg));
match(RegI);
match(mRegI);

format %{ "A4" %}
interface(REG_INTER);
%}

operand mA5RegI() %{
constraint(ALLOC_IN_RC(a5_reg));
match(RegI);
Expand Down Expand Up @@ -3355,6 +3364,16 @@ operand a2_RegP()
interface(REG_INTER);
%}

operand a3_RegP()
%{
constraint(ALLOC_IN_RC(a3_long_reg));
match(RegP);
match(mRegP);

format %{ %}
interface(REG_INTER);
%}

operand a4_RegP()
%{
constraint(ALLOC_IN_RC(a4_long_reg));
Expand Down Expand Up @@ -8008,65 +8027,93 @@ instruct clear_array(a2RegL cnt, a0_RegP base, Universe dummy, a1RegL value) %{
ins_pipe( pipe_slow );
%}

instruct string_compareL(a4_RegP str1, mA5RegI cnt1, a6_RegP str2, mA7RegI cnt2, mRegI result, mRegL tmp1, mRegL tmp2, regF vtmp1, regF vtmp2) %{
instruct string_compareL(a1_RegP str1, mA2RegI cnt1, a3_RegP str2, mA4RegI cnt2,
mA0RegI result, mRegL tmp1, mRegL tmp2,
regF vtmp1, regF vtmp2) %{
predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP vtmp1, TEMP vtmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2);
effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP vtmp1, TEMP vtmp2,
USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2);

format %{ "String Compare byte[] $str1[len: $cnt1], $str2[len: $cnt2] "
"tmp1:$tmp1, tmp2:$tmp2, vtmp1:$vtmp1, vtmp2:$vtmp2 -> "
"$result @ string_compareL" %}

format %{ "String Compare byte[] $str1[len: $cnt1], $str2[len: $cnt2] tmp1:$tmp1, tmp2:$tmp2, vtmp1:$vtmp1, vtmp2:$vtmp2 -> $result @ string_compareL" %}
ins_encode %{
__ string_compare($str1$$Register, $str2$$Register,
$cnt1$$Register, $cnt2$$Register, $result$$Register,
StrIntrinsicNode::LL, $tmp1$$Register, $tmp2$$Register,
$vtmp1$$FloatRegister, $vtmp2$$FloatRegister);
__ string_compareL($str1$$Register, $str2$$Register,
$cnt1$$Register, $cnt2$$Register,
$result$$Register,
$tmp1$$Register, $tmp2$$Register,
$vtmp1$$FloatRegister, $vtmp2$$FloatRegister);
%}

ins_pipe( pipe_slow );
%}

instruct string_compareU(a4_RegP str1, mA5RegI cnt1, a6_RegP str2, mA7RegI cnt2, mRegI result, mRegL tmp1, mRegL tmp2, regF vtmp1, regF vtmp2) %{
instruct string_compareU(a1_RegP str1, mA2RegI cnt1, a3_RegP str2, mA4RegI cnt2,
mA0RegI result, mRegL tmp1, mRegL tmp2,
regF vtmp1, regF vtmp2) %{
predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP vtmp1, TEMP vtmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2);
effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP vtmp1, TEMP vtmp2,
USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2);

format %{ "String Compare byte[] $str1[len: $cnt1], $str2[len: $cnt2] "
"tmp1:$tmp1, tmp2:$tmp2, vtmp1:$vtmp1, vtmp2:$vtmp2 -> "
"$result @ string_compareU" %}

format %{ "String Compare char[] $str1[len: $cnt1], $str2[len: $cnt2] tmp1:$tmp1, tmp2:$tmp2, vtmp1:$vtmp1, vtmp2:$vtmp2 -> $result @ string_compareU" %}
ins_encode %{
__ string_compare($str1$$Register, $str2$$Register,
$cnt1$$Register, $cnt2$$Register, $result$$Register,
StrIntrinsicNode::UU, $tmp1$$Register, $tmp2$$Register,
$vtmp1$$FloatRegister, $vtmp2$$FloatRegister);
__ string_compareU($str1$$Register, $str2$$Register,
$cnt1$$Register, $cnt2$$Register,
$result$$Register,
$tmp1$$Register, $tmp2$$Register,
$vtmp1$$FloatRegister, $vtmp2$$FloatRegister);
%}

ins_pipe( pipe_slow );
%}

instruct string_compareLU(a4_RegP str1, mA5RegI cnt1, a6_RegP str2, mA7RegI cnt2, mRegI result, mRegL tmp1, mRegL tmp2, regF vtmp1, regF vtmp2) %{
instruct string_compareLU(a1_RegP str1, mA2RegI cnt1, a3_RegP str2, mA4RegI cnt2,
mA0RegI result, mRegL tmp1, mRegL tmp2,
regF vtmp1, regF vtmp2) %{
predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP vtmp1, TEMP vtmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2);
effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP vtmp1, TEMP vtmp2,
USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2);

format %{ "String Compare byte[] $str1[len: $cnt1], $str2[len: $cnt2] "
"tmp1:$tmp1, tmp2:$tmp2, vtmp1:$vtmp1, vtmp2:$vtmp2 -> "
"$result @ string_compareLU" %}

format %{ "String Compare byte[] $str1[len: $cnt1], $str2[len: $cnt2] tmp1:$tmp1, tmp2:$tmp2, vtmp1:$vtmp1, vtmp2:$vtmp2 -> $result @ string_compareLU" %}
ins_encode %{
__ string_compare($str1$$Register, $str2$$Register,
$cnt1$$Register, $cnt2$$Register, $result$$Register,
StrIntrinsicNode::LU, $tmp1$$Register, $tmp2$$Register,
$vtmp1$$FloatRegister, $vtmp2$$FloatRegister);
__ string_compareLU($str1$$Register, $str2$$Register,
$cnt1$$Register, $cnt2$$Register,
$result$$Register,
$tmp1$$Register, $tmp2$$Register,
$vtmp1$$FloatRegister, $vtmp2$$FloatRegister);
%}

ins_pipe( pipe_slow );
%}

instruct string_compareUL(a4_RegP str1, mA5RegI cnt1, a6_RegP str2, mA7RegI cnt2, mRegI result, mRegL tmp1, mRegL tmp2, regF vtmp1, regF vtmp2) %{
instruct string_compareUL(a1_RegP str1, mA2RegI cnt1, a3_RegP str2, mA4RegI cnt2,
mA0RegI result, mRegL tmp1, mRegL tmp2,
regF vtmp1, regF vtmp2) %{
predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP vtmp1, TEMP vtmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2);
effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP vtmp1, TEMP vtmp2,
USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2);

format %{ "String Compare byte[] $str1[len: $cnt1], $str2[len: $cnt2] "
"tmp1:$tmp1, tmp2:$tmp2, vtmp1:$vtmp1, vtmp2:$vtmp2 -> "
"$result @ string_compareUL" %}

format %{ "String Compare byte[] $str1[len: $cnt1], $str2[len: $cnt2] tmp1:$tmp1, tmp2:$tmp2, vtmp1:$vtmp1, vtmp2:$vtmp2 -> $result @ string_compareUL" %}
ins_encode %{
__ string_compare($str1$$Register, $str2$$Register,
$cnt1$$Register, $cnt2$$Register, $result$$Register,
StrIntrinsicNode::UL, $tmp1$$Register, $tmp2$$Register,
$vtmp1$$FloatRegister, $vtmp2$$FloatRegister);
__ string_compareUL($str1$$Register, $str2$$Register,
$cnt1$$Register, $cnt2$$Register,
$result$$Register,
$tmp1$$Register, $tmp2$$Register,
$vtmp1$$FloatRegister, $vtmp2$$FloatRegister);
%}

ins_pipe( pipe_slow );
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4 changes: 4 additions & 0 deletions src/hotspot/cpu/loongarch/nativeInst_loongarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -66,6 +66,10 @@ bool NativeInstruction::is_lu12iw_lu32id() const {
Assembler::high(int_at(4), 7) == Assembler::lu32i_d_op;
}

bool NativeInstruction::is_pcaddi() const {
return Assembler::high(int_at(0), 7) == Assembler::pcaddi_op;
}

bool NativeInstruction::is_pcaddu12i_add() const {
return Assembler::high(int_at(0), 7) == Assembler::pcaddu12i_op &&
Assembler::high(int_at(4), 10) == Assembler::addi_d_op;
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1 change: 1 addition & 0 deletions src/hotspot/cpu/loongarch/nativeInst_loongarch.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -75,6 +75,7 @@ class NativeInstruction {
// Helper func for jvmci
bool is_lu12iw_lu32id() const;
bool is_pcaddu12i_add() const;
bool is_pcaddi() const;

// LoongArch has no instruction to generate a illegal instruction exception?
// But `break 11` is not illegal instruction for LoongArch.
Expand Down
167 changes: 0 additions & 167 deletions src/hotspot/os_cpu/linux_loongarch/amcas_asm.h
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