Remove all occurrences of 'mem2array' and 'array2mem'

Replace deprecated commands 'mem2array' and 'array2mem' with new Tcl commands 'read_memory' and 'write_memory'. Change-Id: I116d995995396133ca782b14cce02bd1ab917a4e Signed-off-by: Marc Schink <[email protected]> Reviewed-on: https://review.openocd.org/c/openocd/+/6859 Tested-by: jenkins Reviewed-by: Antonio Borneo <[email protected]>
kevin-gillespie · Mar 12, 2022 · be0d68e · be0d68e
1 parent e370e06
commit be0d68e
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Showing 18 changed files with 79 additions and 123 deletions.
diff --git a/contrib/rpc_examples/ocd_rpc_example.py b/contrib/rpc_examples/ocd_rpc_example.py
@@ -95,24 +95,16 @@ def readVariable(self, address):
         return None if (len(raw) < 2) else strToHex(raw[1])
 
     def readMemory(self, wordLen, address, n):
-        self.send("array unset output") # better to clear the array before
-        self.send("mem2array output %d 0x%x %d" % (wordLen, address, n))
-
-        output = [*map(int, self.send("return $output").split(" "))]
-        d = dict([tuple(output[i:i + 2]) for i in range(0, len(output), 2)])
-
-        return [d[k] for k in sorted(d.keys())]
+        output = self.send("read_memory 0x%x %d %d" % (address, wordLen, n))
+        return [*map(lambda x: int(x, 16), output.split(" "))]
 
     def writeVariable(self, address, value):
         assert value is not None
         self.send("mww 0x%x 0x%x" % (address, value))
 
-    def writeMemory(self, wordLen, address, n, data):
-        array = " ".join(["%d 0x%x" % (a, b) for a, b in enumerate(data)])
-
-        self.send("array unset 1986ве1т") # better to clear the array before
-        self.send("array set 1986ве1т { %s }" % array)
-        self.send("array2mem 1986ве1т 0x%x %s %d" % (wordLen, address, n))
+    def writeMemory(self, wordLen, address, data):
+        data = "{" + ' '.join(['0x%x' % x for x in data]) + "}"
+        self.send("write_memory 0x%x %d %s" % (address, wordLen, data))
 
 if __name__ == "__main__":
 

diff --git a/tcl/board/at91cap7a-stk-sdram.cfg b/tcl/board/at91cap7a-stk-sdram.cfg
@@ -32,8 +32,7 @@ $_TARGETNAME configure -event reset-start {
 }
 
 proc peek32 {address} {
-	mem2array t 32 $address 1
-	return $t(0)
+	return [read_memory $address 32 1]
 }
 
 # Wait for an expression to be true with a timeout

diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg
@@ -40,9 +40,7 @@ at91sam9 rdy_busy 0 0xfffff800 13
 at91sam9 ce 0 0xfffff800 14
 
 proc read_register {register} {
-        set result ""
-        mem2array result 32 $register 1
-        return $result(0)
+	return [read_memory $register 32 1]
 }
 
 proc at91sam9g20_reset_start { } {

diff --git a/tcl/board/embedded-artists_lpc2478-32.cfg b/tcl/board/embedded-artists_lpc2478-32.cfg
@@ -8,9 +8,7 @@ source [find target/lpc2478.cfg]
 # Helper
 #
 proc read_register {register} {
-    set result ""
-    mem2array result 32 $register 1
-    return $result(0)
+    return [read_memory $register 32 1]
 }
 
 proc init_board {} {

diff --git a/tcl/board/hilscher_nxhx10.cfg b/tcl/board/hilscher_nxhx10.cfg
@@ -26,9 +26,7 @@ proc flash_init { } {
 }
 
 proc mread32 {addr} {
-  set value(0) 0
-  mem2array value 32 $addr 1
-  return $value(0)
+  return [read_memory $addr 32 1]
 }
 
 proc init_clocks { } {

diff --git a/tcl/board/icnova_sam9g45_sodimm.cfg b/tcl/board/icnova_sam9g45_sodimm.cfg
@@ -43,9 +43,7 @@ flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
 
 
 proc read_register {register} {
-        set result ""
-        mem2array result 32 $register 1
-        return $result(0)
+	return [read_memory $register 32 1]
 }
 
 proc at91sam9g45_start { } {

diff --git a/tcl/chip/atmel/at91/aic.tcl b/tcl/chip/atmel/at91/aic.tcl
@@ -54,36 +54,36 @@ proc show_AIC_IMR_helper { NAME ADDR VAL } {
 
 proc show_AIC { } {
     global AIC_SMR
-    if [catch { mem2array aaa 32 $AIC_SMR [expr {32 * 4}] } msg ] {
+    if [catch { set aaa [read_memory $AIC_SMR 32 [expr {32 * 4}]] } msg ] {
 	error [format "%s (%s)" $msg AIC_SMR]
     }
     echo "AIC_SMR: Mode & Type"
     global AT91C_ID
     for { set x 0 } { $x < 32 } {  } {
 	echo -n "   "
-	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
+	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
 	incr x
-	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
+	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
 	incr x
-	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
+	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
 	incr x
-	echo  [format "%2d: %5s 0x%08x"  $x $AT91C_ID($x) $aaa($x)]
+	echo  [format "%2d: %5s 0x%08x"  $x $AT91C_ID($x) [lindex $aaa $x]]
 	incr x
     }
     global AIC_SVR
-    if [catch { mem2array aaa 32 $AIC_SVR [expr {32 * 4}] } msg ] {
+    if [catch { set aaa [read_memory $AIC_SVR 32 [expr {32 * 4}]] } msg ] {
 	error [format "%s (%s)" $msg AIC_SVR]
     }
     echo "AIC_SVR: Vectors"
     for { set x 0 } { $x < 32 } {  } {
 	echo -n "   "
-	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
+	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
 	incr x
-	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
+	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
 	incr x
-	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
+	echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
 	incr x
-	echo [format "%2d: %5s 0x%08x" $x $AT91C_ID($x) $aaa($x)]
+	echo [format "%2d: %5s 0x%08x" $x $AT91C_ID($x) [lindex $aaa $x]]
 	incr x
     }
 

diff --git a/tcl/cpu/arc/common.tcl b/tcl/cpu/arc/common.tcl
@@ -29,9 +29,8 @@ proc arc_common_reset { {target ""} } {
         # vector located at the interrupt vector base address, which is the first
         # entry (offset 0x00) in the vector table.
         set int_vector_base [arc jtag get-aux-reg 0x25]
-        set start_pc ""
-        mem2array start_pc 32 $int_vector_base 1
-        arc jtag set-aux-reg 0x6 $start_pc(0)
+        set start_pc [read_memory $int_vector_base 32 1]
+        arc jtag set-aux-reg 0x6 $start_pc
 
         # It is OK to do uncached writes - register cache will be invalidated by
         # the reset_assert() function.

diff --git a/tcl/mem_helper.tcl b/tcl/mem_helper.tcl
@@ -2,29 +2,23 @@
 
 # mrw: "memory read word", returns value of $reg
 proc mrw {reg} {
-	set value ""
-	mem2array value 32 $reg 1
-	return $value(0)
+	return [read_memory $reg 32 1]
 }
 
 add_usage_text mrw "address"
 add_help_text mrw "Returns value of word in memory."
 
 # mrh: "memory read halfword", returns value of $reg
 proc mrh {reg} {
-	set value ""
-	mem2array value 16 $reg 1
-	return $value(0)
+	return [read_memory $reg 16 1]
 }
 
 add_usage_text mrh "address"
 add_help_text mrh "Returns value of halfword in memory."
 
 # mrb: "memory read byte", returns value of $reg
 proc mrb {reg} {
-	set value ""
-	mem2array value 8 $reg 1
-	return $value(0)
+	return [read_memory $reg 8 1]
 }
 
 add_usage_text mrb "address"

diff --git a/tcl/memory.tcl b/tcl/memory.tcl
@@ -79,108 +79,96 @@ proc address_info { ADDRESS } {
 }
 
 proc memread32 {ADDR} {
-    set foo(0) 0
-    if ![ catch { mem2array foo 32 $ADDR 1  } msg ] {
-	return $foo(0)
+    if ![ catch { set foo [read_memory $ADDR 32 1] } msg ] {
+	return $foo
     } else {
 	error "memread32: $msg"
     }
 }
 
 proc memread16 {ADDR} {
-    set foo(0) 0
-    if ![ catch { mem2array foo 16 $ADDR 1  } msg ] {
-	return $foo(0)
+    if ![ catch { set foo [read_memory $ADDR 16 1] } msg ] {
+	return $foo
     } else {
 	error "memread16: $msg"
     }
 }
 
 proc memread8 {ADDR} {
-    set foo(0) 0
-    if ![ catch { mem2array foo 8 $ADDR 1  } msg ] {
-	return $foo(0)
+    if ![ catch { set foo [read_memory $ADDR 8 1] } msg ] {
+	return $foo
     } else {
 	error "memread8: $msg"
     }
 }
 
 proc memwrite32 {ADDR DATA} {
-    set foo(0) $DATA
-    if ![ catch { array2mem foo 32 $ADDR 1  } msg ] {
-	return $foo(0)
+    if ![ catch { write_memory $ADDR 32 $DATA } msg ] {
+	return $DATA
     } else {
 	error "memwrite32: $msg"
     }
 }
 
 proc memwrite16 {ADDR DATA} {
-    set foo(0) $DATA
-    if ![ catch { array2mem foo 16 $ADDR 1  } msg ] {
-	return $foo(0)
+    if ![ catch { write_memory $ADDR 16 $DATA } msg ] {
+	return $DATA
     } else {
 	error "memwrite16: $msg"
     }
 }
 
 proc memwrite8 {ADDR DATA} {
-    set foo(0) $DATA
-    if ![ catch { array2mem foo 8 $ADDR 1  } msg ] {
-	return $foo(0)
+    if ![ catch { write_memory $ADDR 8 $DATA } msg ] {
+	return $DATA
     } else {
 	error "memwrite8: $msg"
     }
 }
 
 proc memread32_phys {ADDR} {
-    set foo(0) 0
-    if ![ catch { mem2array foo 32 $ADDR 1 phys } msg ] {
-	return $foo(0)
+    if ![ catch { set foo [read_memory $ADDR 32 1 phys] } msg ] {
+	return $foo
     } else {
 	error "memread32: $msg"
     }
 }
 
 proc memread16_phys {ADDR} {
-    set foo(0) 0
-    if ![ catch { mem2array foo 16 $ADDR 1 phys } msg ] {
-	return $foo(0)
+    if ![ catch { set foo [read_memory $ADDR 16 1 phys] } msg ] {
+	return $foo
     } else {
 	error "memread16: $msg"
     }
 }
 
 proc memread8_phys {ADDR} {
-    set foo(0) 0
-    if ![ catch { mem2array foo 8 $ADDR 1 phys } msg ] {
-	return $foo(0)
+    if ![ catch { set foo [read_memory $ADDR 8 1 phys] } msg ] {
+	return $foo
     } else {
 	error "memread8: $msg"
     }
 }
 
 proc memwrite32_phys {ADDR DATA} {
-    set foo(0) $DATA
-    if ![ catch { array2mem foo 32 $ADDR 1 phys } msg ] {
-	return $foo(0)
+    if ![ catch { write_memory $ADDR 32 $DATA phys } msg ] {
+	return $DATA
     } else {
 	error "memwrite32: $msg"
     }
 }
 
 proc memwrite16_phys {ADDR DATA} {
-    set foo(0) $DATA
-    if ![ catch { array2mem foo 16 $ADDR 1 phys } msg ] {
-	return $foo(0)
+    if ![ catch { write_memory $ADDR 16 $DATA phys } msg ] {
+	return $DATA
     } else {
 	error "memwrite16: $msg"
     }
 }
 
 proc memwrite8_phys {ADDR DATA} {
-    set foo(0) $DATA
-    if ![ catch { array2mem foo 8 $ADDR 1 phys } msg ] {
-	return $foo(0)
+    if ![ catch { write_memory $ADDR 8 $DATA phys } msg ] {
+	return $DATA
     } else {
 	error "memwrite8: $msg"
     }

diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl
@@ -29,9 +29,7 @@ source [find mem_helper.tcl]
 
 # read a 64-bit register (memory mapped)
 proc mr64bit {reg} {
-    set value ""
-    mem2array value 32 $reg 2
-    return $value
+    return [read_memory $reg 32 2]
 }
 
 
@@ -117,19 +115,19 @@ proc showAmbaClk {} {
     set PLL_CLK_BYPASS	             [regs PLL_CLK_BYPASS]
 
     echo [format "CLKCORE_AHB_CLK_CNTRL       (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]]
-    mem2array value 32 $CLKCORE_AHB_CLK_CNTRL 1
+    set value [read_memory $CLKCORE_AHB_CLK_CNTRL 32 1]
     # see if the PLL is in bypass mode
-    set bypass [expr {($value(0) & $PLL_CLK_BYPASS) >> 24}]
+    set bypass [expr {($value & $PLL_CLK_BYPASS) >> 24}]
     echo [format "PLL bypass bit: %d" $bypass]
     if {$bypass == 1} {
 	echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]]
     } else {
 	# nope, extract x,y,w and compute the PLL output freq.
-	set x [expr {($value(0) & 0x0001F0000) >> 16}]
+	set x [expr {($value & 0x0001F0000) >> 16}]
 	echo [format "x: %d" $x]
-	set y [expr {($value(0) & 0x00000007F)}]
+	set y [expr {($value & 0x00000007F)}]
 	echo [format "y: %d" $y]
-	set w [expr {($value(0) & 0x000000300) >> 8}]
+	set w [expr {($value & 0x000000300) >> 8}]
 	echo [format "w: %d" $w]
 	echo [format "Amba PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]
     }
@@ -192,19 +190,19 @@ proc showArmClk {} {
     set PLL_CLK_BYPASS	        [regs PLL_CLK_BYPASS]
 
     echo [format "CLKCORE_ARM_CLK_CNTRL       (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]]
-    mem2array value 32 $CLKCORE_ARM_CLK_CNTRL 1
+    set value [read_memory $CLKCORE_ARM_CLK_CNTRL 32 1]
     # see if the PLL is in bypass mode
-    set bypass [expr {($value(0) & $PLL_CLK_BYPASS) >> 24}]
+    set bypass [expr {($value & $PLL_CLK_BYPASS) >> 24}]
     echo [format "PLL bypass bit: %d" $bypass]
     if {$bypass == 1} {
 	echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]]
     } else {
 	# nope, extract x,y,w and compute the PLL output freq.
-	set x [expr {($value(0) & 0x0001F0000) >> 16}]
+	set x [expr {($value & 0x0001F0000) >> 16}]
 	echo [format "x: %d" $x]
-	set y [expr {($value(0) & 0x00000007F)}]
+	set y [expr {($value & 0x00000007F)}]
 	echo [format "y: %d" $y]
-	set w [expr {($value(0) & 0x000000300) >> 8}]
+	set w [expr {($value & 0x000000300) >> 8}]
 	echo [format "w: %d" $w]
 	echo [format "Arm PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]
     }

diff --git a/tcl/target/hilscher_netx500.cfg b/tcl/target/hilscher_netx500.cfg
@@ -26,9 +26,7 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
 
 proc mread32 {addr} {
-  set value(0) 0
-  mem2array value 32 $addr 1
-  return $value(0)
+  return [read_memory $addr 32 1]
 }
 
 # This function must be called on netX100/500 right after halt