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code style fixes
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@felipesanches
felipesanches committed Dec 26, 2023
1 parent df6daa7 commit e36b253
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Showing 8 changed files with 113 additions and 138 deletions.
8 changes: 5 additions & 3 deletions src/devices/bus/technics/hdae5000.h
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Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,10 @@
//
// HD-AE5000 emulation
//
#ifndef MAME_BUS_HD_AE5000_H
#define MAME_BUS_HD_AE5000_H
#ifndef MAME_BUS_TECHNICS_HDAE5000_H
#define MAME_BUS_TECHNICS_HDAE5000_H

#pragma once

#include "kn5000_extension.h"
#include "bus/ata/hdd.h"
Expand Down Expand Up @@ -33,4 +35,4 @@ class hdae5000_device : public device_t, public kn5000_extension_interface

DECLARE_DEVICE_TYPE(HDAE5000, hdae5000_device)

#endif
#endif // MAME_BUS_TECHNICS_HDAE5000_H
2 changes: 1 addition & 1 deletion src/devices/bus/technics/kn5000_extension.h
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// license:BSD-3-Clause
// copyright-holders:Olivier Galibert, Felipe Sanches

//
// Generic Technics KN5000 extension slot

#ifndef MAME_BUS_TECHNICS_KN5000_EXTENSION_H
Expand Down
82 changes: 41 additions & 41 deletions src/devices/cpu/tlcs900/dasm900.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1462,11 +1462,11 @@ const char *const tmp95c061_disassembler::s_sfr_names[0x80] = {
};

tmp95c063_disassembler::tmp95c063_disassembler()
: tlcs900_disassembler(0xA0, s_sfr_names)
: tlcs900_disassembler(0xa0, s_sfr_names)
{
}

const char *const tmp95c063_disassembler::s_sfr_names[0xA0] = {
const char *const tmp95c063_disassembler::s_sfr_names[0xa0] = {
/*00:*/ "0x00", "P1", "0x02", "0x03", "P1CR", "0x05", "P2", "0x07",
/*08:*/ "0x08", "P2FC", "0x0a", "0x0b", "0x0c", "P5", "0x0e", "0x0f",
/*10:*/ "P5CR", "P5FC", "P6", "P7", "0x14", "P6FC", "P7CR", "P7FC",
Expand Down Expand Up @@ -1593,7 +1593,7 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const
case M_C0:
switch( op & 0x07 )
{
case 0x00: /* 0xC0 */
case 0x00: /* 0xc0 */
imm = opcodes.r8( pos++ );
if (imm < m_num_sfr){
buf = string_format("%s", m_sfr_names[imm]);
Expand All @@ -1602,7 +1602,7 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const
}
break;

case 0x01: /* 0xC1 */
case 0x01: /* 0xc1 */
imm = opcodes.r8( pos++ );
imm = imm | (opcodes.r8( pos++ ) << 8);
if (imm < m_num_sfr){
Expand All @@ -1612,7 +1612,7 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const
}
break;

case 0x02: /* 0xC2 */
case 0x02: /* 0xc2 */
imm = opcodes.r8( pos++ );
imm = imm | (opcodes.r8( pos++ ) << 8);
imm = imm | (opcodes.r8( pos++ ) << 16);
Expand All @@ -1623,7 +1623,7 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const
}
break;

case 0x03: /* 0xC3 */
case 0x03: /* 0xc3 */
imm = opcodes.r8( pos++ );
switch( imm & 0x03 )
{
Expand Down Expand Up @@ -1667,12 +1667,12 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const
}
break;

case 0x04: /* 0xC4 */
case 0x04: /* 0xc4 */
imm = opcodes.r8( pos++ );
buf = string_format("-%s", s_allreg32[imm]);
break;

case 0x05: /* 0xC5 */
case 0x05: /* 0xc5 */
imm = opcodes.r8( pos++ );
buf = string_format("%s+", s_allreg32[imm]);
break;
Expand All @@ -1698,25 +1698,25 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const
case M_D0:
switch( op & 0x07 )
{
case 0x00: /* 0xD0 */
case 0x00: /* 0xd0 */
imm = opcodes.r8( pos++ );
buf = string_format("0x%02x", imm);
break;

case 0x01: /* 0xD1 */
case 0x01: /* 0xd1 */
imm = opcodes.r8( pos++ );
imm = imm | (opcodes.r8( pos++ ) << 8);
buf = string_format("0x%04x", imm);
break;

case 0x02: /* 0xD2 */
case 0x02: /* 0xd2 */
imm = opcodes.r8( pos++ );
imm = imm | (opcodes.r8( pos++ ) << 8);
imm = imm | (opcodes.r8( pos++ ) << 16);
buf = string_format("0x%06x", imm);
break;

case 0x03: /* 0xD3 */
case 0x03: /* 0xd3 */
imm = opcodes.r8( pos++ );
switch( imm & 0x03 )
{
Expand Down Expand Up @@ -1760,12 +1760,12 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const
}
break;

case 0x04: /* 0xD4 */
case 0x04: /* 0xd4 */
imm = opcodes.r8( pos++ );
buf = string_format("-%s", s_allreg32[imm]);
break;

case 0x05: /* 0xD5 */
case 0x05: /* 0xd5 */
imm = opcodes.r8( pos++ );
buf = string_format("%s+", s_allreg32[imm]);
break;
Expand All @@ -1792,25 +1792,25 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const
case M_E0:
switch( op & 0x07 )
{
case 0x00: /* 0xE0 */
case 0x00: /* 0xe0 */
imm = opcodes.r8( pos++ );
buf = string_format("0x%02x", imm);
break;

case 0x01: /* 0xE1 */
case 0x01: /* 0xe1 */
imm = opcodes.r8( pos++ );
imm = imm | (opcodes.r8( pos++ ) << 8);
buf = string_format("0x%04x", imm);
break;

case 0x02: /* 0xE2 */
case 0x02: /* 0xe2 */
imm = opcodes.r8( pos++ );
imm = imm | (opcodes.r8( pos++ ) << 8);
imm = imm | (opcodes.r8( pos++ ) << 16);
buf = string_format("0x%06x", imm);
break;

case 0x03: /* 0xE3 */
case 0x03: /* 0xe3 */
imm = opcodes.r8( pos++ );
switch( imm & 0x03 )
{
Expand Down Expand Up @@ -1854,12 +1854,12 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const
}
break;

case 0x04: /* 0xE4 */
case 0x04: /* 0xe4 */
imm = opcodes.r8( pos++ );
buf = string_format("-%s", s_allreg32[imm]);
break;

case 0x05: /* 0xE5 */
case 0x05: /* 0xe5 */
imm = opcodes.r8( pos++ );
buf = string_format("%s+", s_allreg32[imm]);
break;
Expand All @@ -1885,7 +1885,7 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const
case M_F0:
switch( op & 0x07 )
{
case 0x00: /* 0xF0 */
case 0x00: /* 0xf0 */
imm = opcodes.r8( pos++ );
if (imm < m_num_sfr){
buf = string_format("%s", m_sfr_names[imm]);
Expand All @@ -1894,7 +1894,7 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const
}
break;

case 0x01: /* 0xF1 */
case 0x01: /* 0xf1 */
imm = opcodes.r8( pos++ );
imm = imm | (opcodes.r8( pos++ ) << 8);
if (imm < m_num_sfr){
Expand All @@ -1904,7 +1904,7 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const
}
break;

case 0x02: /* 0xF2 */
case 0x02: /* 0xf2 */
imm = opcodes.r8( pos++ );
imm = imm | (opcodes.r8( pos++ ) << 8);
imm = imm | (opcodes.r8( pos++ ) << 16);
Expand All @@ -1915,7 +1915,7 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const
}
break;

case 0x03: /* 0xF3 */
case 0x03: /* 0xf3 */
imm = opcodes.r8( pos++ );
switch( imm & 0x03 )
{
Expand Down Expand Up @@ -1959,12 +1959,12 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const
}
break;

case 0x04: /* 0xF4 */
case 0x04: /* 0xf4 */
imm = opcodes.r8( pos++ );
buf = string_format("-%s", s_allreg32[imm]);
break;

case 0x05: /* 0xF5 */
case 0x05: /* 0xf5 */
imm = opcodes.r8( pos++ );
buf = string_format("%s+", s_allreg32[imm]);
break;
Expand Down Expand Up @@ -2054,7 +2054,7 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const

case O_CR32:
imm = opcodes.r8( pos++ );
switch (imm & 0xe3)
switch( imm & 0xe3 )
{
case 0x00:
util::stream_format(stream, " DMAS%d", (imm >> 2) & 7);
Expand All @@ -2070,13 +2070,13 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const

case O_D8:
imm = opcodes.r8( pos++ );
util::stream_format(stream, " 0x%06x", ( pos + (int8_t)imm ) & 0xFFFFFF);
util::stream_format(stream, " 0x%06x", ( pos + (int8_t)imm ) & 0xffffff);
break;

case O_D16:
imm = opcodes.r8( pos++ );
imm = imm | (opcodes.r8( pos++ ) << 8);
util::stream_format(stream, " 0x%06x", ( pos + (int16_t)imm ) & 0xFFFFFF);
util::stream_format(stream, " 0x%06x", ( pos + (int16_t)imm ) & 0xffffff);
break;

case O_F:
Expand Down Expand Up @@ -2188,55 +2188,55 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const

case O_CR8:
imm = opcodes.r8( pos++ );
switch (imm & 0xe3)
switch( imm & 0xe3 )
{
case 0x42:
util::stream_format(stream, ", DMAM%d", (imm >> 2) & 7);
util::stream_format(stream, ",DMAM%d", (imm >> 2) & 7);
break;
default:
util::stream_format(stream, ", <Unknown 8-bit ControlReg 0x%02X>", imm);
util::stream_format(stream, ",<Unknown 8-bit ControlReg 0x%02X>", imm);
break;
}
break;

case O_CR16:
imm = opcodes.r8( pos++ );
switch (imm & 0xe3)
switch( imm & 0xe3 )
{
case 0x40:
util::stream_format(stream, ", DMAC%d", (imm >> 2) & 7);
util::stream_format(stream, ",DMAC%d", (imm >> 2) & 7);
break;
default:
util::stream_format(stream, ", <Unknown 16-bit ControlReg 0x%02X>", imm);
util::stream_format(stream, ",<Unknown 16-bit ControlReg 0x%02X>", imm);
break;
}
break;

case O_CR32:
imm = opcodes.r8( pos++ );
switch (imm & 0xe3)
switch( imm & 0xe3 )
{
case 0x00:
util::stream_format(stream, ", DMAS%d", (imm >> 2) & 7);
util::stream_format(stream, ",DMAS%d", (imm >> 2) & 7);
break;
case 0x20:
util::stream_format(stream, ", DMAD%d", (imm >> 2) & 7);
util::stream_format(stream, ",DMAD%d", (imm >> 2) & 7);
break;
default:
util::stream_format(stream, ", <Unknown 32-bit ControlReg 0x%02X>", imm);
util::stream_format(stream, ",<Unknown 32-bit ControlReg 0x%02X>", imm);
break;
}
break;

case O_D8:
imm = opcodes.r8( pos++ );
util::stream_format(stream, ",0x%06x", ( pos + (int8_t)imm ) & 0xFFFFFF);
util::stream_format(stream, ",0x%06x", ( pos + (int8_t)imm ) & 0xffffff);
break;

case O_D16:
imm = opcodes.r8( pos++ );
imm = imm | (opcodes.r8( pos++ ) << 8);
util::stream_format(stream, ",0x%06x", ( pos + (int16_t)imm ) & 0xFFFFFF);
util::stream_format(stream, ",0x%06x", ( pos + (int16_t)imm ) & 0xffffff);
break;

case O_F:
Expand Down
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