RISC-V: Remove unused StarFive debug options

These three options should have been removed with the cache flushing code in the different drivers that was replaced by Atish' generic non-coherent dma solution: CONFIG_USB_CDNS3_HOST_FLUSH_DMA CONFIG_FPGA_GMAC_FLUSH_DDR CONFIG_MMC_DW_FLUSH_DDR Signed-off-by: Emil Renner Berthing <[email protected]>
esmil · Jun 23, 2021 · 18f0e8a · 18f0e8a
1 parent 5185b2c
commit 18f0e8a
Showing 1 changed file with 0 additions and 25 deletions.
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
@@ -35,31 +35,6 @@ config SOC_STARFIVE_VIC7100
 menu "StarFive VIC7100 SoC Debug Option"
 	depends on SOC_STARFIVE_VIC7100
 
-config FPGA_GMAC_FLUSH_DDR
-	bool "VIC7100 SOC GMAC description and packet buffer flush"
-	depends on SOC_STARFIVE_VIC7100
-	depends on STMMAC_ETH
-	default y if SOC_STARFIVE_VIC7100
-	help
-	  enable VIC7100 GMAC description and packet buffer flush
-
-config MMC_DW_FLUSH_DDR
-	bool "VIC7100 SOC DW MMC buffer flush"
-	depends on SOC_STARFIVE_VIC7100
-	depends on MMC_DW
-	default y if SOC_STARFIVE_VIC7100
-	help
-	  enable VIC7100 DW MMC description and data buffer flush
-
-config USB_CDNS3_HOST_FLUSH_DMA
-	bool "Cadence USB3 host controller flush dma memery"
-	depends on USB
-	depends on USB_CDNS3
-	depends on SOC_STARFIVE_VIC7100
-	default y if SOC_STARFIVE_VIC7100
-	help
-	  enable VIC7100 DW USB CDNS3 driver data buffer flush
-
 config SOC_STARFIVE_VIC7100_I2C_GPIO
 	bool "VIC7100 SOC I2C GPIO init"
 	depends on I2C_DESIGNWARE_CORE