This project is an experiment where we make two rings with the same number of stages but measure how their frequency differs.
As we can enable one at a time or both we can also measure if they can influence eachother.
With the clock running, after reset, assert trigger. Counter will keep track of number of ring positive edges. This can be used to infer the average number of ring periods inside one scan clock period. Use sel bits to get result
TinyTapeout is an educational project that aims to make it easier and cheaper than ever to get your digital designs manufactured on a real chip!
Go to https://tinytapeout.com for instructions!
Edit the info.yaml and change the wokwi_id to match your project.
Please see the instructions for:
When you edit the info.yaml to choose a different ID, the GitHub Action will fetch the digital netlist of your design from Wokwi.
After that, the action uses the open source ASIC tool called OpenLane to build the files needed to fabricate an ASIC.
- Share your GDS on Twitter, tag it #tinytapeout and link me!