dont move stores before loads to respect WL

dag_in_context/src/optimizations/mem_simple.egg

@@ -57,7 +57,7 @@
 
 (relation DidMemOptimization (String))
 
-; A write and a load to different addresses can be swapped
+; A write then a load to different addresses can be swapped
 (rule ((NoAlias write-addr load-addr)
        (= write (Top (Write) write-addr write-val state))
        (= load (Bop (Load) load-addr write)))
@@ -71,16 +71,18 @@
       :ruleset mem-simple)
 
 ; A load then a write to different addresses can be swapped
-(rule ((NoAlias load-addr write-addr)
-       (= load (Bop (Load) load-addr state))
-       (= write (Top (Write) write-addr write-val (Get load 1))))
-      ((let new-write (Top (Write) write-addr write-val state))
-       (let new-load (Bop (Load) load-addr new-write))
-       (union write (Get new-load 1))
-       (union (Get load 0) (Get new-load 0))
-       (DidMemOptimization "commute load then write")
-       )
-      :ruleset mem-simple)
+; Actually, does this break WeaklyLinear if the stored value depends on the
+; loaded value? Commenting this out for now.
+; (rule ((NoAlias load-addr write-addr)
+;        (= load (Bop (Load) load-addr state))
+;        (= write (Top (Write) write-addr write-val (Get load 1))))
+;       ((let new-write (Top (Write) write-addr write-val state))
+;        (let new-load (Bop (Load) load-addr new-write))
+;        (union write (Get new-load 1))
+;        (union (Get load 0) (Get new-load 0))
+;        (DidMemOptimization "commute load then write")
+;        )
+;       :ruleset mem-simple)
 
 ; Two loads to the same address can be compressed
 (rule ((= first-load (Bop (Load) addr state))

tests/snapshots/files__fib-2-optimize.snap

@@ -46,18 +46,18 @@ expression: visualization.result
   v8_: int = id v14_;
   v9_: int = id v15_;
   v10_: int = id v16_;
-  c31_: int = const -1;
-  v32_: int = add c31_ v8_;
-  v33_: ptr<int> = ptradd v7_ v32_;
+  v31_: ptr<int> = ptradd v7_ v8_;
+  c32_: int = const -1;
+  v33_: ptr<int> = ptradd v31_ c32_;
   v34_: int = load v33_;
   free v7_;
   print v34_;
   ret;
   jmp .b35_;
 .b12_:
-  c31_: int = const -1;
-  v32_: int = add c31_ v8_;
-  v33_: ptr<int> = ptradd v7_ v32_;
+  v31_: ptr<int> = ptradd v7_ v8_;
+  c32_: int = const -1;
+  v33_: ptr<int> = ptradd v31_ c32_;
   v34_: int = load v33_;
   free v7_;
   print v34_;