fix vcs compilation error

efabless · Jul 9, 2024 · ff4aa9c · ff4aa9c
1 parent 1f99038
commit ff4aa9c
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Showing 4 changed files with 16 additions and 14 deletions.
diff --git a/EF_I2C.yaml b/EF_I2C.yaml
@@ -7,7 +7,7 @@ info:
   license: APACHE 2.0
   author: Mohamed Shalan
   email: [email protected]
-  version: v1.0.7
+  version: v1.0.8
   date: 09-07-2024
   category: digital
   tags:

diff --git a/hdl/rtl/bus_wrappers/EF_I2C_APB.pp.v b/hdl/rtl/bus_wrappers/EF_I2C_APB.pp.v
@@ -75,16 +75,6 @@ module EF_I2C_APB # (
     localparam[15:0] GCLK_REG_ADDR = 16'hFF10;
 
     reg [0:0] GCLK_REG;
-	always @(posedge PCLK or negedge PRESETn) if(~PRESETn) GCLK_REG <= 0;
-                                        else if(apb_we & (PADDR[15:0]==GCLK_REG_ADDR)) begin
-                                            GCLK_REG <= PWDATA[1-1:0];
-                                            apb_wr_ack <= 1;
-                                        end else if(apb_valid & (PADDR[15:0]==GCLK_REG_ADDR))
-                                            apb_rd_ack <= 1;
-                                        else begin
-                                            apb_wr_ack <= 0;
-                                            apb_rd_ack <= 0;
-                                        end
 
         wire clk_g;
         wire clk_gated_en = GCLK_REG[0];
@@ -169,7 +159,18 @@ module EF_I2C_APB # (
 
         .flags(flags)
     );
-
+
+	always @(posedge PCLK or negedge PRESETn) if(~PRESETn) GCLK_REG <= 0;
+                                        else if(apb_we & (PADDR[15:0]==GCLK_REG_ADDR)) begin
+                                            GCLK_REG <= PWDATA[1-1:0];
+                                            apb_wr_ack <= 1;
+                                        end else if(apb_valid & (PADDR[15:0]==GCLK_REG_ADDR))
+                                            apb_rd_ack <= 1;
+                                        else begin
+                                            apb_wr_ack <= 0;
+                                            apb_rd_ack <= 0;
+                                        end
+
     always @(posedge PCLK or negedge PRESETn) if(~PRESETn) IM_REG <= 0;
                                         else if(apb_we & (PADDR[15:0]==IM_REG_ADDR)) begin
                                             IM_REG <= PWDATA[9-1:0];

diff --git a/hdl/rtl/bus_wrappers/EF_I2C_APB.v b/hdl/rtl/bus_wrappers/EF_I2C_APB.v
@@ -75,7 +75,6 @@ module EF_I2C_APB # (
     localparam[15:0] GCLK_REG_ADDR = 16'hFF10;
 
     reg [0:0] GCLK_REG;
-	`APB_REG(GCLK_REG, 0, 1)
 
         wire clk_g;
         wire clk_gated_en = GCLK_REG[0];
@@ -160,7 +159,9 @@ module EF_I2C_APB # (
 
         .flags(flags)
     );
-
+
+	`APB_REG(GCLK_REG, 0, 1)
+
     `APB_REG(IM_REG, 0, 9)
 
     assign i2c_irq = |MIS_REG;

diff --git a/v1.0.7.tar.gz b/v1.0.7.tar.gz