added gated clock

efabless · Jul 9, 2024 · cc9a339 · cc9a339
1 parent e97b3fd
commit cc9a339
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Showing 6 changed files with 72 additions and 5 deletions.
diff --git a/EF_I2C.yaml b/EF_I2C.yaml
@@ -7,8 +7,8 @@ info:
   license: APACHE 2.0
   author: Mohamed Shalan
   email: [email protected]
-  version: v1.0.5
-  date: 08-07-2024
+  version: v1.0.6
+  date: 09-07-2024
   category: digital
   tags:
   - peripheral

diff --git a/fw/EF_I2C.c b/fw/EF_I2C.c
@@ -3,6 +3,11 @@
 
 #include <EF_I2C.h>
 
+void EF_I2C_setGclkEnable (uint32_t i2c_base, int value){
+    EF_I2C_TYPE* i2c = (EF_I2C_TYPE*)i2c_base;
+    i2c->GCLK = value;
+}
+
 void EF_I2C_writeToAddress(uint32_t i2c_base, char addr, char data){
     EF_I2C_writeData(i2c_base, data);
     EF_I2C_writeCmd(i2c_base, addr);

diff --git a/fw/EF_I2C.h b/fw/EF_I2C.h
@@ -5,7 +5,7 @@
 #include <stdint.h>
 #include <stdbool.h>
 
-
+void EF_I2C_setGclkEnable (uint32_t i2c_base, int value);
 void EF_I2C_writeAddress(uint32_t i2c_base, char addr);
 void EF_I2C_startCmd(uint32_t i2c_base);
 void EF_I2C_readCmd(uint32_t i2c_base, char addr);

diff --git a/fw/EF_I2C_regs.h b/fw/EF_I2C_regs.h
@@ -66,6 +66,7 @@ typedef struct _EF_I2C_TYPE_ {
 	__RW	IM;
 	__R 	MIS;
 	__R 	RIS;
+	__W 	GCLK;
 } EF_I2C_TYPE;
 
 

diff --git a/hdl/rtl/bus_wrappers/EF_I2C_APB.pp.v b/hdl/rtl/bus_wrappers/EF_I2C_APB.pp.v
@@ -41,6 +41,10 @@ module EF_I2C_APB # (
     parameter READ_FIFO = 1,
     parameter READ_FIFO_DEPTH = 16
 ) (
+`ifdef USE_POWER_PINS 
+	inout VPWR,
+	inout VGND,
+`endif
     input wire          PCLK,
     input wire          PRESETn,
 
@@ -68,8 +72,38 @@ module EF_I2C_APB # (
     localparam[15:0] RIS_REG_ADDR = 16'hFF08;
     localparam[15:0] IM_REG_ADDR = 16'hFF00;
     localparam[15:0] MIS_REG_ADDR = 16'hFF04;
+    localparam[15:0] GCLK_REG_ADDR = 16'hFF10;
+
+    reg [0:0] GCLK_REG;
+	always @(posedge PCLK or negedge PRESETn) if(~PRESETn) GCLK_REG <= 0;
+                                        else if(apb_we & (PADDR[15:0]==GCLK_REG_ADDR)) begin
+                                            GCLK_REG <= PWDATA[1-1:0];
+                                            apb_wr_ack <= 1;
+                                        end else if(apb_valid & (PADDR[15:0]==GCLK_REG_ADDR))
+                                            apb_rd_ack <= 1;
+                                        else begin
+                                            apb_wr_ack <= 0;
+                                            apb_rd_ack <= 0;
+                                        end
+
+        wire clk_g;
+        wire clk_gated_en = GCLK_REG[0];
+
+    (* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
+    `ifdef USE_POWER_PINS 
+        .VPWR(VPWR), 
+        .VGND(VGND), 
+        .VNB(VGND),
+		.VPB(VPWR),
+    `endif 
+        .GCLK(clk_g), 
+        .GATE(clk_gated_en), 
+        .CLK(PCLK)
+        );
+
+	wire		clk = clk_g;
+	wire		rst_n = PRESETn;
 
-    wire                clk         = PCLK;
     wire                rst         = ~PRESETn;
     wire [ 2:0]         wbs_adr_i   = PADDR[3:1];
     wire [15:0]         wbs_dat_i   = PWDATA[15:0];
@@ -95,6 +129,7 @@ module EF_I2C_APB # (
                     (PADDR[15:0] == RIS_REG_ADDR)   ? {23'b0, RIS_REG}  :
                     (PADDR[15:0] == MIS_REG_ADDR)   ? {23'b0, MIS_REG}  :
                     (PADDR[15:0] == IM_REG_ADDR)    ? {23'b0, IM_REG}   :
+                    (PADDR[15:0] == GCLK_REG_ADDR)  ? {23'b0, GCLK_REG}   :
                     32'hDEADBEEF;
 
     i2c_master_wbs_16 #

diff --git a/hdl/rtl/bus_wrappers/EF_I2C_APB.v b/hdl/rtl/bus_wrappers/EF_I2C_APB.v
@@ -41,6 +41,10 @@ module EF_I2C_APB # (
     parameter READ_FIFO = 1,
     parameter READ_FIFO_DEPTH = 16
 ) (
+    `ifdef USE_POWER_PINS
+	inout VPWR,
+	inout VGND,
+    `endif
     input wire          PCLK,
     input wire          PRESETn,
 
@@ -68,8 +72,29 @@ module EF_I2C_APB # (
     localparam[15:0] RIS_REG_ADDR = 16'hFF08;
     localparam[15:0] IM_REG_ADDR = 16'hFF00;
     localparam[15:0] MIS_REG_ADDR = 16'hFF04;
+    localparam[15:0] GCLK_REG_ADDR = 16'hFF10;
+
+    reg [0:0] GCLK_REG;
+	`APB_REG(GCLK_REG, 0, 1)
+
+        wire clk_g;
+        wire clk_gated_en = GCLK_REG[0];
+
+    (* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
+    `ifdef USE_POWER_PINS 
+        .VPWR(VPWR), 
+        .VGND(VGND), 
+        .VNB(VGND),
+		.VPB(VPWR),
+    `endif 
+        .GCLK(clk_g), 
+        .GATE(clk_gated_en), 
+        .CLK(PCLK)
+        );
+
+	wire		clk = clk_g;
+	wire		rst_n = PRESETn;
 
-    wire                clk         = PCLK;
     wire                rst         = ~PRESETn;
     wire [ 2:0]         wbs_adr_i   = PADDR[3:1];
     wire [15:0]         wbs_dat_i   = PWDATA[15:0];
@@ -95,6 +120,7 @@ module EF_I2C_APB # (
                     (PADDR[15:0] == RIS_REG_ADDR)   ? {23'b0, RIS_REG}  :
                     (PADDR[15:0] == MIS_REG_ADDR)   ? {23'b0, MIS_REG}  :
                     (PADDR[15:0] == IM_REG_ADDR)    ? {23'b0, IM_REG}   :
+                    (PADDR[15:0] == GCLK_REG_ADDR)  ? {23'b0, GCLK_REG}   :
                     32'hDEADBEEF;
 
     i2c_master_wbs_16 #