style(Message): more robust issue isolation (OpenXiangShan#315)

src/main/scala/coupledL2/RequestArb.scala

@@ -217,7 +217,7 @@ class RequestArb(implicit p: Parameters) extends L2Module
     task_s2.bits.toTXREQ && (
       task_s2.bits.chiOpcode.get === WriteBackFull ||
       task_s2.bits.chiOpcode.get === WriteEvictFull ||
-      task_s2.bits.chiOpcode.get === WriteEvictOrEvict && afterIssueE.B ||
+      onIssueEbOrElse(task_s2.bits.chiOpcode.get === WriteEvictOrEvict, false.B) ||
       task_s2.bits.chiOpcode.get === Evict
     )
   } else {

src/main/scala/coupledL2/tl2chi/MMIOBridge.scala

@@ -169,7 +169,7 @@ class MMIOBridgeEntry(edge: TLEdgeIn)(implicit p: Parameters) extends TL2CHIL2Mo
     }
     when (
       rxrsp.bits.opcode === CompDBIDResp || rxrsp.bits.opcode === DBIDResp ||
-      ENABLE_ISSUE_Eb.B && rxrsp.bits.opcode === DBIDRespOrd
+      onIssueEbOrElse(rxrsp.bits.opcode === DBIDRespOrd, false.B)
     ) {
       w_dbidresp := true.B
       srcID := rxrsp.bits.srcID

src/main/scala/coupledL2/tl2chi/MSHR.scala

@@ -326,7 +326,7 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
   val isWriteCleanFull = req_cboClean
   val isWriteBackFull = !req_cboClean && !req_cboInval && (isT(meta.state) && meta.dirty || probeDirty)
   val isWriteEvictFull = false.B
-  val isWriteEvictOrEvict = !isWriteCleanFull && !isWriteBackFull && !isWriteEvictFull && afterIssueE.B
+  val isWriteEvictOrEvict = onIssueEbOrElse(!isWriteCleanFull && !isWriteBackFull && !isWriteEvictFull, false.B)
   val isEvict = !isWriteCleanFull && !isWriteBackFull && !isWriteEvictFull && !isWriteEvictOrEvict
   val a_task = {
     val oa = io.tasks.txreq.bits
@@ -353,7 +353,7 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
       (release_valid2 && isWriteCleanFull)               -> WriteCleanFull,
       (release_valid2 && isWriteBackFull)                -> WriteBackFull,
       (release_valid2 && isWriteEvictFull)               -> WriteEvictFull,
-      (release_valid2 && isWriteEvictOrEvict)            -> WriteEvictOrEvict,
+      (release_valid2 && isWriteEvictOrEvict)            -> onIssueEbOrElse(WriteEvictOrEvict, DontCare),
       (release_valid2 && isEvict)                        -> Evict,
       req_cboClean                                       -> CleanShared,
       req_cboFlush                                       -> CleanInvalid,
@@ -461,7 +461,7 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
     mp_release.chiOpcode.get := ParallelPriorityMux(Seq(
       isWriteBackFull       -> WriteBackFull,
       isWriteEvictFull      -> WriteEvictFull,
-      isWriteEvictOrEvict   -> WriteEvictOrEvict,
+      isWriteEvictOrEvict   -> onIssueEbOrElse(WriteEvictOrEvict, DontCare),
       isEvict /* Default */ -> Evict
     ))
     mp_release.resp.get := 0.U // DontCare
@@ -868,8 +868,6 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
   Seq(
     ("CopyBackWrData", CHICohStateTransSet.ofCopyBackWrData(CopyBackWrData)),
     ("CompData", CHICohStateTransSet.ofCompData(CompData)),
-    ("DataSepResp", CHICohStateTransSet.ofDataSepResp(DataSepResp)),
-    ("RespSepData", CHICohStateTransSet.ofRespSepData(RespSepData)),
     ("SnpResp", CHICohStateTransSet.ofSnpResp(SnpResp)),
     ("SnpRespData", CHICohStateTransSet.ofSnpRespData(SnpRespData)),
     ("SnpRespDataPtl", CHICohStateTransSet.ofSnpRespDataPtl(SnpRespDataPtl)),
@@ -881,6 +879,17 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
       s"invalid Resp for ${name}")
   }}
 
+  ifIssueEb {
+    Seq(
+      ("DataSepResp", CHICohStateTransSet.ofDataSepResp(DataSepResp)),
+      ("RespSepData", CHICohStateTransSet.ofRespSepData(RespSepData))
+    ).foreach { case (name, set) => {
+      assert(!mp_valid || CHICohStateTransSet.isValid(set, 
+          mp.txChannel, mp.chiOpcode.get, mp.resp.get),
+        s"invalid Resp for ${name}")
+    }}
+  }
+
   /* ======== Assertions for DCT forwarded snoop ======== */
   Seq(
     ("SnpRespFwded", CHICohStateFwdedTransSet.ofSnpRespFwded(SnpRespFwded)),
@@ -993,16 +1002,18 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
   when (rxdat.valid) {
     val nderr = rxdat.bits.respErr.getOrElse(OK) === NDERR
     val derr = rxdat.bits.respErr.getOrElse(OK) === DERR
-    when (rxdat.bits.chiOpcode.get === DataSepResp) {
-      require(beatSize == 2) // TODO: This is ugly
-      beatCnt := beatCnt + 1.U
-      state.w_grantfirst := true.B
-      state.w_grantlast := state.w_grantfirst && beatCnt === (beatSize - 1).U
-      gotT := rxdatIsU || rxdatIsU_PD
-      gotDirty := gotDirty || rxdatIsU_PD
-      gotGrantData := true.B
-      denied := denied || nderr
-      corrupt := corrupt || derr || nderr
+    ifIssueEb {
+      when (rxdat.bits.chiOpcode.get === DataSepResp) {
+        require(beatSize == 2) // TODO: This is ugly
+        beatCnt := beatCnt + 1.U
+        state.w_grantfirst := true.B
+        state.w_grantlast := state.w_grantfirst && beatCnt === (beatSize - 1).U
+        gotT := rxdatIsU || rxdatIsU_PD
+        gotDirty := gotDirty || rxdatIsU_PD
+        gotGrantData := true.B
+        denied := denied || nderr
+        corrupt := corrupt || derr || nderr
+      }
     }
 
     when (rxdat.bits.chiOpcode.get === CompData) {
@@ -1024,13 +1035,15 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
   // RXRSP
   when (rxrsp.valid) {
     val nderr = rxrsp.bits.respErr.getOrElse(OK) === NDERR
-    when (rxrsp.bits.chiOpcode.get === RespSepData) {
-      state.w_grant := true.B
-      srcid := rxrsp.bits.srcID.getOrElse(0.U)
-      homenid := rxrsp.bits.srcID.getOrElse(0.U)
-      dbid := rxrsp.bits.dbID.getOrElse(0.U)
-      denied := denied || nderr
-      req.traceTag.get := rxrsp.bits.traceTag.get
+    ifIssueEb {
+      when (rxrsp.bits.chiOpcode.get === RespSepData) {
+        state.w_grant := true.B
+        srcid := rxrsp.bits.srcID.getOrElse(0.U)
+        homenid := rxrsp.bits.srcID.getOrElse(0.U)
+        dbid := rxrsp.bits.dbID.getOrElse(0.U)
+        denied := denied || nderr
+        req.traceTag.get := rxrsp.bits.traceTag.get
+      }
     }
 
     when (rxrsp.bits.chiOpcode.get === Comp) {

src/main/scala/coupledL2/tl2chi/MainPipe.scala

@@ -183,7 +183,8 @@ class MainPipe(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes
   val mshr_writeCleanFull_s3    = mshr_req_s3 && req_s3.toTXREQ && req_s3.chiOpcode.get === WriteCleanFull
   val mshr_writeBackFull_s3     = mshr_req_s3 && req_s3.toTXREQ && req_s3.chiOpcode.get === WriteBackFull
   val mshr_writeEvictFull_s3    = mshr_req_s3 && req_s3.toTXREQ && req_s3.chiOpcode.get === WriteEvictFull
-  val mshr_writeEvictOrEvict_s3 = mshr_req_s3 && req_s3.toTXREQ && req_s3.chiOpcode.get === WriteEvictOrEvict && afterIssueE.B
+  val mshr_writeEvictOrEvict_s3 = mshr_req_s3 && req_s3.toTXREQ &&
+    onIssueEbOrElse(req_s3.chiOpcode.get === WriteEvictOrEvict, false.B)
   val mshr_evict_s3             = mshr_req_s3 && req_s3.toTXREQ && req_s3.chiOpcode.get === Evict
 
   val mshr_cbWrData_s3          = mshr_req_s3 && req_s3.toTXDAT && req_s3.chiOpcode.get === CopyBackWrData

src/main/scala/coupledL2/tl2chi/TXDAT.scala

@@ -164,7 +164,8 @@ class TXDAT(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
     dat.be := be
     dat.data := deassertData(beat, be)
     dat.resp := task.resp.get
-    dat.fwdState := task.fwdState.get
+    // dat.fwdState := task.fwdState.get
+    dat.setFwdState(task.fwdState.get)
     dat.traceTag := task.traceTag.get
     dat.dataCheck := dataCheck
     dat.poision := Fill(POISON_WIDTH, task.corrupt)

src/main/scala/coupledL2/tl2chi/chi/LinkLayer.scala

@@ -174,8 +174,11 @@ class LCredit2Decoupled[T <: Bundle](
   } else {
     var lsb = 0
     queue.io.enq.bits.getElements.reverse.foreach { case e =>
-      e := io.in.flit.asUInt(lsb + e.asUInt.getWidth - 1, lsb).asTypeOf(e.cloneType)
-      lsb += e.asUInt.getWidth
+    val elementWidth = e.asUInt.getWidth
+    if (elementWidth > 0) {
+        e := io.in.flit.asUInt(lsb + elementWidth - 1, lsb).asTypeOf(e.cloneType)
+        lsb += elementWidth
+    }
     }
   }