Bug-fix: remove hardcoded widths used in pktbuf addressing

crossroadsfpga · Mar 16, 2022 · 87b0e91 · 87b0e91
1 parent b060b4f
commit 87b0e91
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Showing 11 changed files with 69 additions and 96 deletions.
diff --git a/pigasus.py b/pigasus.py
@@ -544,8 +544,8 @@ def struct_s():
 app.add_extern("out_empty", 6, Direction.OUTPUT)
 app.add_extern("out_ready", 1, Direction.INPUT)
 app.add_extern("pkt_buf_wren", 1, Direction.OUTPUT)
-app.add_extern("pkt_buf_wraddress", 17, Direction.OUTPUT)
-app.add_extern("pkt_buf_rdaddress", 17, Direction.OUTPUT)
+app.add_extern("pkt_buf_wraddress", "PKTBUF_AWIDTH", Direction.OUTPUT)
+app.add_extern("pkt_buf_rdaddress", "PKTBUF_AWIDTH", Direction.OUTPUT)
 app.add_extern("pkt_buf_wrdata", 520, Direction.OUTPUT)
 app.add_extern("pkt_buf_rden", 1, Direction.OUTPUT)
 app.add_extern("pkt_buf_rd_valid", 1, Direction.INPUT)

diff --git a/pigasus/hardware/rtl_sim/src/buffer/esram_wrapper.sv b/pigasus/hardware/rtl_sim/src/buffer/esram_wrapper.sv
@@ -1,28 +1,26 @@
 `include "./src/struct_s.sv"
 
 module esram_wrapper(
-    input   logic           clk_esram_ref, // 100 MHz
-    output  logic           esram_pll_lock,
+    input   logic                       clk_esram_ref, // 100 MHz
+    output  logic                       esram_pll_lock,
 `ifdef USE_BRAM
-    input   logic           clk_esram, // 200 MHz
+    input   logic                       clk_esram, // 200 MHz
 `elsif SIM
-    input   logic           clk_esram, // 200 MHz
+    input   logic                       clk_esram, // 200 MHz
 `else
-    output  logic           clk_esram, // 200 MHz
+    output  logic                       clk_esram, // 200 MHz
 `endif
-    input   logic           wren,
-    input   logic [16:0]    wraddress,
-    input   logic [519:0]   wrdata,
-    input   logic           rden,
-    input   logic [16:0]    rdaddress,
-    output  logic           rd_valid,
-    output  logic [519:0]   rddata
+    input   logic                       wren,
+    input   logic [PKTBUF_AWIDTH-1:0]   wraddress,
+    input   logic [519:0]               wrdata,
+    input   logic                       rden,
+    input   logic [PKTBUF_AWIDTH-1:0]   rdaddress,
+    output  logic                       rd_valid,
+    output  logic [519:0]               rddata
 );
 
 // In simulation, we just use a big BRAM to accelerate simulation speed.
 `ifdef USE_BRAM
-localparam DEPTH = (PKT_NUM*32);
-localparam AWIDTH = ($clog2(DEPTH));
 
 logic rden_r;
 assign esram_pll_lock = 1;
@@ -34,9 +32,9 @@ always @(posedge clk_esram) begin
 end
 
 bram_simple2port #(
-    .AWIDTH(AWIDTH),
+    .AWIDTH(PKTBUF_AWIDTH),
     .DWIDTH(520),
-    .DEPTH(DEPTH)
+    .DEPTH(PKTBUF_DEPTH)
 )
 esrm_sim (
     .clock     (clk_esram),

diff --git a/pigasus/hardware/rtl_sim/src/tb.sv b/pigasus/hardware/rtl_sim/src/tb.sv
@@ -125,19 +125,14 @@ logic           ddr_rd_resp_valid_int;
 
 
 //eSRAM signals
-logic esram_pll_lock; 
-logic         esram_pkt_buf_wren;
-`ifdef USE_BRAM
-logic [14:0]  pkt_buf_wraddress;
-logic [14:0]  pkt_buf_rdaddress;
-`else
-logic [16:0]  pkt_buf_wraddress;
-logic [16:0]  pkt_buf_rdaddress;
-`endif
-logic [519:0] pkt_buf_wrdata;
-logic         pkt_buf_rden;
-logic         pkt_buf_rd_valid;
-logic [519:0] pkt_buf_rddata;
+logic                       esram_pll_lock;
+logic                       esram_pkt_buf_wren;
+logic [PKTBUF_AWIDTH-1:0]   pkt_buf_wraddress;
+logic [PKTBUF_AWIDTH-1:0]   pkt_buf_rdaddress;
+logic [519:0]               pkt_buf_wrdata;
+logic                       pkt_buf_rden;
+logic                       pkt_buf_rd_valid;
+logic [519:0]               pkt_buf_rddata;
 
 //JTAG
 logic [29:0] s_addr;

diff --git a/pigasus/hardware/rtl_sim/src/top.sv b/pigasus/hardware/rtl_sim/src/top.sv
@@ -22,8 +22,8 @@ module top (
     output logic [5:0] out_empty,
     input logic [0:0] out_ready,
     output logic [0:0] pkt_buf_wren,
-    output logic [16:0] pkt_buf_wraddress,
-    output logic [16:0] pkt_buf_rdaddress,
+    output logic [PKTBUF_AWIDTH-1:0] pkt_buf_wraddress,
+    output logic [PKTBUF_AWIDTH-1:0] pkt_buf_rdaddress,
     output logic [519:0] pkt_buf_wrdata,
     output logic [0:0] pkt_buf_rden,
     input logic [0:0] pkt_buf_rd_valid,

diff --git a/pigasus/hardware/scripts/src/alt_ehipc2_hw.sv b/pigasus/hardware/scripts/src/alt_ehipc2_hw.sv
@@ -350,20 +350,15 @@ module alt_ehipc2_hw (
     logic [31:0]     fc_1_readdata;
 
     //eSRAM signals
-    logic            clk_datamover;
-    logic            rst_datamover;
-    logic            pkt_buf_wren;
-`ifdef USE_BRAM
-    logic [14:0]     pkt_buf_rdaddress;
-    logic [14:0]     pkt_buf_wraddress;
-`else
-    logic [16:0]     pkt_buf_rdaddress;
-    logic [16:0]     pkt_buf_wraddress;
-`endif
-    logic [519:0]    pkt_buf_wrdata;
-    logic            pkt_buf_rden;
-    logic            pkt_buf_rd_valid;
-    logic [519:0]    pkt_buf_rddata;
+    logic                       clk_datamover;
+    logic                       rst_datamover;
+    logic                       pkt_buf_wren;
+    logic [PKTBUF_AWIDTH-1:0]   pkt_buf_rdaddress;
+    logic [PKTBUF_AWIDTH-1:0]   pkt_buf_wraddress;
+    logic [519:0]               pkt_buf_wrdata;
+    logic                       pkt_buf_rden;
+    logic                       pkt_buf_rd_valid;
+    logic [519:0]               pkt_buf_rddata;
 
     //PCIe signal
     logic            pcie_clk;

diff --git a/pigasus_multi.py b/pigasus_multi.py
@@ -569,8 +569,8 @@ def struct_s():
 app.add_extern("out_1_empty", 6, Direction.OUTPUT)
 app.add_extern("out_1_ready", 1, Direction.INPUT)
 app.add_extern("pkt_buf_wren", 1, Direction.OUTPUT)
-app.add_extern("pkt_buf_wraddress", 17, Direction.OUTPUT)
-app.add_extern("pkt_buf_rdaddress", 17, Direction.OUTPUT)
+app.add_extern("pkt_buf_wraddress", "PKTBUF_AWIDTH", Direction.OUTPUT)
+app.add_extern("pkt_buf_rdaddress", "PKTBUF_AWIDTH", Direction.OUTPUT)
 app.add_extern("pkt_buf_wrdata", 520, Direction.OUTPUT)
 app.add_extern("pkt_buf_rden", 1, Direction.OUTPUT)
 app.add_extern("pkt_buf_rd_valid", 1, Direction.INPUT)
@@ -629,8 +629,8 @@ def struct_s():
 app1.add_extern("out_1_empty", 6, Direction.OUTPUT)
 app1.add_extern("out_1_ready", 1, Direction.INPUT)
 app1.add_extern("pkt_buf_wren", 1, Direction.OUTPUT)
-app1.add_extern("pkt_buf_wraddress", 17, Direction.OUTPUT)
-app1.add_extern("pkt_buf_rdaddress", 17, Direction.OUTPUT)
+app1.add_extern("pkt_buf_wraddress", "PKTBUF_AWIDTH", Direction.OUTPUT)
+app1.add_extern("pkt_buf_rdaddress", "PKTBUF_AWIDTH", Direction.OUTPUT)
 app1.add_extern("pkt_buf_wrdata", 520, Direction.OUTPUT)
 app1.add_extern("pkt_buf_rden", 1, Direction.OUTPUT)
 app1.add_extern("pkt_buf_rd_valid", 1, Direction.INPUT)

diff --git a/pigasus_multi/rtl_sim/tb.sv b/pigasus_multi/rtl_sim/tb.sv
@@ -132,19 +132,14 @@ logic           ddr_rd_resp_valid_int;
 
 
 //eSRAM signals
-logic esram_pll_lock; 
-logic         esram_pkt_buf_wren;
-`ifdef USE_BRAM
-logic [14:0]  pkt_buf_wraddress;
-logic [14:0]  pkt_buf_rdaddress;
-`else
-logic [16:0]  pkt_buf_wraddress;
-logic [16:0]  pkt_buf_rdaddress;
-`endif
-logic [519:0] pkt_buf_wrdata;
-logic         pkt_buf_rden;
-logic         pkt_buf_rd_valid;
-logic [519:0] pkt_buf_rddata;
+logic                       esram_pll_lock;
+logic                       esram_pkt_buf_wren;
+logic [PKTBUF_AWIDTH-1:0]   pkt_buf_wraddress;
+logic [PKTBUF_AWIDTH-1:0]   pkt_buf_rdaddress;
+logic [519:0]               pkt_buf_wrdata;
+logic                       pkt_buf_rden;
+logic                       pkt_buf_rd_valid;
+logic [519:0]               pkt_buf_rddata;
 
 //JTAG
 logic [29:0] s_addr;

diff --git a/pigasus_multi/rtl_sim/top_0.sv b/pigasus_multi/rtl_sim/top_0.sv
@@ -29,8 +29,8 @@ module top_0 (
     output logic [5:0] out_1_empty,
     input logic [0:0] out_1_ready,
     output logic [0:0] pkt_buf_wren,
-    output logic [16:0] pkt_buf_wraddress,
-    output logic [16:0] pkt_buf_rdaddress,
+    output logic [PKTBUF_AWIDTH-1:0] pkt_buf_wraddress,
+    output logic [PKTBUF_AWIDTH-1:0] pkt_buf_rdaddress,
     output logic [519:0] pkt_buf_wrdata,
     output logic [0:0] pkt_buf_rden,
     input logic [0:0] pkt_buf_rd_valid,

diff --git a/pigasus_multi/rtl_sim/top_1.sv b/pigasus_multi/rtl_sim/top_1.sv
@@ -29,8 +29,8 @@ module top_1 (
     output logic [5:0] out_1_empty,
     input logic [0:0] out_1_ready,
     output logic [0:0] pkt_buf_wren,
-    output logic [16:0] pkt_buf_wraddress,
-    output logic [16:0] pkt_buf_rdaddress,
+    output logic [PKTBUF_AWIDTH-1:0] pkt_buf_wraddress,
+    output logic [PKTBUF_AWIDTH-1:0] pkt_buf_rdaddress,
     output logic [519:0] pkt_buf_wrdata,
     output logic [0:0] pkt_buf_rden,
     input logic [0:0] pkt_buf_rd_valid,

diff --git a/pigasus_multi/scripts/src_0/alt_ehipc2_hw.sv b/pigasus_multi/scripts/src_0/alt_ehipc2_hw.sv
@@ -355,20 +355,15 @@ module alt_ehipc2_hw (
     logic [31:0]     fc_1_readdata;
 
     //eSRAM signals
-    logic            clk_datamover;
-    logic            rst_datamover;
-    logic            pkt_buf_wren;
-`ifdef USE_BRAM
-    logic [14:0]     pkt_buf_rdaddress;
-    logic [14:0]     pkt_buf_wraddress;
-`else
-    logic [16:0]     pkt_buf_rdaddress;
-    logic [16:0]     pkt_buf_wraddress;
-`endif
-    logic [519:0]    pkt_buf_wrdata;
-    logic            pkt_buf_rden;
-    logic            pkt_buf_rd_valid;
-    logic [519:0]    pkt_buf_rddata;
+    logic                       clk_datamover;
+    logic                       rst_datamover;
+    logic                       pkt_buf_wren;
+    logic [PKTBUF_AWIDTH-1:0]   pkt_buf_rdaddress;
+    logic [PKTBUF_AWIDTH-1:0]   pkt_buf_wraddress;
+    logic [519:0]               pkt_buf_wrdata;
+    logic                       pkt_buf_rden;
+    logic                       pkt_buf_rd_valid;
+    logic [519:0]               pkt_buf_rddata;
 
     //PCIe signal
     logic            pcie_clk;

diff --git a/pigasus_multi/scripts/src_1/alt_ehipc2_hw.sv b/pigasus_multi/scripts/src_1/alt_ehipc2_hw.sv
@@ -355,20 +355,15 @@ module alt_ehipc2_hw (
     logic [31:0]     fc_1_readdata;
 
     //eSRAM signals
-    logic            clk_datamover;
-    logic            rst_datamover;
-    logic            pkt_buf_wren;
-`ifdef USE_BRAM
-    logic [14:0]     pkt_buf_rdaddress;
-    logic [14:0]     pkt_buf_wraddress;
-`else
-    logic [16:0]     pkt_buf_rdaddress;
-    logic [16:0]     pkt_buf_wraddress;
-`endif
-    logic [519:0]    pkt_buf_wrdata;
-    logic            pkt_buf_rden;
-    logic            pkt_buf_rd_valid;
-    logic [519:0]    pkt_buf_rddata;
+    logic                       clk_datamover;
+    logic                       rst_datamover;
+    logic                       pkt_buf_wren;
+    logic [PKTBUF_AWIDTH-1:0]   pkt_buf_rdaddress;
+    logic [PKTBUF_AWIDTH-1:0]   pkt_buf_wraddress;
+    logic [519:0]               pkt_buf_wrdata;
+    logic                       pkt_buf_rden;
+    logic                       pkt_buf_rd_valid;
+    logic [519:0]               pkt_buf_rddata;
 
     //PCIe signal
     logic            pcie_clk;