Fix to sync_nent signal for in memories

cms-L1TK · Jun 5, 2024 · 8eae0d0 · 8eae0d0
1 parent 2db1c98
commit 8eae0d0
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py
@@ -644,7 +644,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl
             portlist += "        addrb     => "+mem+"_V_readaddr,\n"
             portlist += "        doutb     => "+mem+"_V_dout,\n"
         if ("AS" in mem or "MPAR" in mem) and "in" in mem:
-            portlist += "        sync_nent => "+mem+"_start,\n"
+            portlist += "        sync_nent => PC_start,\n"
         elif "MPAR" in mem and "in" not in mem:
             portlist += "        sync_nent => "+mem+"_start,\n"
         else: