Merge/stream synchronization

[mcoshiro]

Fixes a few synchronization issues in FPGA 1 project

• tf_merge_streamer now only read TP_bx_out when it is valid so BX 0 is synchronized with other BXs
• tf_merge_streamer now outputs its own BX output (TP_bx_out_merged) which is synchronized with its outputs
• tf_merge_streamer read location is now synchronized with the appropriate valid bit, which fixes occasional strange behavior

It was noticed that some of the output does not match the test vectors, but this seems to be caused by TPs upstream of the merge/stream step.

Associated with PR #64 in project_generation_scripts.

[mcoshiro]

Expanding scope of PR: now added additional changes to help FPGA1 project to meet timing. Two main changes are included:

Changed TPAR memories to use URAMs

This helps with high BRAM usage since currently all the TPARs must be placed near TP_L1L2A as the done signal for all TPARs comes from this single TP. This change makes the baseline project workable, but long term, we will need to change this as additional TPARs for displaced tracking will make the current solution untenable

Modified tf_merge_streamer

Vivado synthesized the previous version of tf_merge_streamer in a way that would generate paths with 20-30 logic levels. In particular, Vivado seemed to struggle to figure out that the for loop with exit could be implemented as a small number of LUTs. I wasn't able to figure out a way that both had clean VHDL and which Vivado could figure out, so for now, I changed it to a rather ugly long if-statement, which Vivado seems to handle better. Other suggestions are welcome.

[jasonfan393]

@mcoshiro looks good, I'd want to simplify the big if block if possible, but if this proves to be too annoying we can always merge this and push it off for later

[jasonfan393]

Looks good! approved