[cover] add line+cond+fsm+tgl+branch+assert into cover report

Signed-off-by: Clo91eaf <[email protected]>
chipsalliance · Jan 16, 2025 · 2b3e595 · 2b3e595
1 parent 41529ec
commit 2b3e595
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/nix/t1/run/default.nix b/nix/t1/run/default.nix
@@ -98,7 +98,7 @@ let
     cp -vr $emuOutput $out
     chmod -R u+w $out
 
-    ${vcs-emu.snps-fhs-env}/bin/snps-fhs-env -c "urg -dir $emuOutput/*/cm.vdb -format text -metric line+tgl+assert -show summary"
+    ${vcs-emu.snps-fhs-env}/bin/snps-fhs-env -c "urg -dir $emuOutput/*/cm.vdb -format text -metric line+cond+fsm+tgl+branch+assert -show summary"
     cp -vr urgReport $out/
   '';
 in

diff --git a/nix/t1/run/run-vcs-emu.nix b/nix/t1/run/run-vcs-emu.nix
@@ -20,7 +20,7 @@ stdenvNoCC.mkDerivation (rec {
   name = "${testCase.pname}-vcs-result" + (lib.optionalString emulator.enableTrace "-trace");
   nativeBuildInputs = [ zstd jq python3 ];
   __noChroot = true;
-  coverType = "line+tgl+assert";
+  coverType = "line+cond+fsm+tgl+branch+assert";
 
   passthru = {
     caseName = testCase.pname;