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Merge branch 'chipsalliance:master' into master
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caryr authored Sep 26, 2024
2 parents e212902 + 5cb96c8 commit 758e232
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Showing 25 changed files with 175 additions and 85 deletions.
28 changes: 4 additions & 24 deletions .github/workflows/comment-pr.yml
Original file line number Diff line number Diff line change
Expand Up @@ -19,29 +19,10 @@ jobs:
run: |
apt-get update -qq
apt install -y unzip
- name: Download artifacts
id: get-artifacts
uses: actions/[email protected]
with:
script: |
var artifacts = await github.actions.listWorkflowRunArtifacts({
owner: context.repo.owner,
repo: context.repo.repo,
run_id: ${{ github.event.workflow_run.id }},
});
var matchArtifact = artifacts.data.artifacts.filter((artifact) => {
return artifact.name == "tests_summary"
})[0];
var download = await github.actions.downloadArtifact({
owner: context.repo.owner,
repo: context.repo.repo,
artifact_id: matchArtifact.id,
archive_format: 'zip',
});
console.log("::set-output name=artifact_id::" + matchArtifact.id);
var fs = require('fs');
fs.writeFileSync('${{github.workspace}}/tests_summary.zip', Buffer.from(download.data));
- uses: actions/download-artifact@v4
with:
name: tests_summary

- name: Unpack artifacts
run: |
Expand All @@ -50,9 +31,8 @@ jobs:
- name: Generate and append artifacts link
run: |
ARTIFACT_ID=${{ steps.get-artifacts.outputs.artifact_id}}
SUITE_ID=$(cat ./suite_id)
ARTIFACT_URL="https://github.com/chipsalliance/sv-tests/suites/$SUITE_ID/artifacts/$ARTIFACT_ID"
ARTIFACT_URL="https://github.com/chipsalliance/sv-tests/suites/$SUITE_ID"
MD_URL="[Download an archive containing all the details]($ARTIFACT_URL)"
echo -e "\n\n$MD_URL" >> tests_summary.md
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32 changes: 5 additions & 27 deletions .github/workflows/lint-review.yml
Original file line number Diff line number Diff line change
@@ -1,38 +1,16 @@
name: lint-review
on:
workflow_run:
workflows: ["trigger-lint"]
types:
- completed
pull_request:

jobs:
lint_review:
runs-on: ubuntu-latest
permissions:
checks: write
contents: read
pull-requests: write
steps:
- uses: actions/checkout@v2
- name: 'Download artifact'
id: get-artifacts
uses: actions/[email protected]
with:
script: |
var artifacts = await github.actions.listWorkflowRunArtifacts({
owner: context.repo.owner,
repo: context.repo.repo,
run_id: ${{github.event.workflow_run.id }},
});
var matchArtifact = artifacts.data.artifacts.filter((artifact) => {
return artifact.name == "event.json"
})[0];
var download = await github.actions.downloadArtifact({
owner: context.repo.owner,
repo: context.repo.repo,
artifact_id: matchArtifact.id,
archive_format: 'zip',
});
var fs = require('fs');
fs.writeFileSync('${{github.workspace}}/event.json.zip', Buffer.from(download.data));
- run: |
unzip event.json.zip
- name: Run Verible action
uses: chipsalliance/verible-linter-action@main
with:
Expand Down
10 changes: 6 additions & 4 deletions .github/workflows/sv-tests-ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,8 @@ jobs:
- name: sv-parser
deps: cargo
rust_ver: "1.74"
- name: tree-sitter-systemverilog
deps: gcc
- name: tree-sitter-verilog
deps: npm
- name: verible
Expand Down Expand Up @@ -176,7 +178,7 @@ jobs:
- name: Pack results
run: |
tar -cvf out_${{ matrix.tool.name }}.tar ./out/report/${{ matrix.tool.name }}_report.csv ./out/logs/
- uses: actions/upload-artifact@v2
- uses: actions/upload-artifact@v4
with:
name: report_${{ matrix.tool.name }}
path: |
Expand Down Expand Up @@ -212,7 +214,7 @@ jobs:
- name: Prepare output directories
run: |
mkdir -p out/report
- uses: actions/download-artifact@v2
- uses: actions/download-artifact@v4
with:
path: ./out/
- name: Extract
Expand Down Expand Up @@ -257,7 +259,7 @@ jobs:
cat $CHANGES_SUMMARY_MD > $GITHUB_STEP_SUMMARY
- name: Upload artifacts for summary
uses: actions/upload-artifact@v2
uses: actions/upload-artifact@v4
if: github.event_name == 'pull_request'
with:
name: tests_summary
Expand All @@ -276,7 +278,7 @@ jobs:
echo $artifacts
- name: Delete Old Artifacts
if: github.event_name == 'pull_request'
uses: geekyeggo/delete-artifact@v1
uses: geekyeggo/delete-artifact@v5
with:
name: ${{ steps.get-artifacts-to-delete.outputs.artifacts }}
Automerge:
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17 changes: 0 additions & 17 deletions .github/workflows/trigger-lint.yml

This file was deleted.

3 changes: 3 additions & 0 deletions .gitmodules
Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,9 @@
[submodule "third_party/tools/tree-sitter-verilog"]
path = third_party/tools/tree-sitter-verilog
url = https://github.com/tree-sitter/tree-sitter-verilog
[submodule "third_party/tools/tree-sitter-systemverilog"]
path = third_party/tools/tree-sitter-systemverilog
url = https://github.com/gmlarumbe/tree-sitter-systemverilog
[submodule "third_party/cores/fx68k"]
path = third_party/cores/fx68k
url = https://github.com/ijor/fx68k
Expand Down
1 change: 1 addition & 0 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -102,6 +102,7 @@ Finally the file containing the test case and metadata should be placed in `test
* [Icarus](http://iverilog.icarus.com)
* [slang](https://github.com/MikePopoloski/slang)
* [sv2v(zachjs)](https://github.com/zachjs/sv2v)
* [tree-sitter-systemverilog](https://github.com/gmlarumbe/tree-sitter-systemverilog)
* [tree-sitter-verilog](https://github.com/tree-sitter/tree-sitter-verilog)
* [sv-parser](https://github.com/dalance/sv-parser)
* [moore](http://llhd.io)
Expand Down
1 change: 1 addition & 0 deletions conf/generators/meta-path/hdlconvertor_std2017.json
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,7 @@
"p188_3.sv",
"p191.sv",
"p196_2.sv",
"p197.sv",
"p201.sv",
"p220.sv",
"p221.sv",
Expand Down
1 change: 1 addition & 0 deletions conf/requirements.txt
Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,7 @@ make_var
markupsafe
pytablewriter
GitPython
simplesat==0.8.2
git+https://github.com/lowRISC/edalize.git@ot
git+https://github.com/lowRISC/fusesoc.git@ot
orderedmultidict
2 changes: 2 additions & 0 deletions generators/ivtest
Original file line number Diff line number Diff line change
Expand Up @@ -279,6 +279,8 @@ ivtest_file_exclude = [
'pr1698659',
'pr2076425',
'shellho1',
# needs data text file that this test harness doesn't enable finding
'pr2800985a',
# primitive table rows are invalid, fails on multiple commercial tools
"pr3587570",
]
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26 changes: 26 additions & 0 deletions tests/chapter-11/11.4.12--concat_op-bit_select.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,26 @@
// Copyright (C) 2019-2021 The SymbiFlow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier: ISC


/*
:name: concat_op-bit_select
:description: concatenation operator w/ bit selection test
:tags: 11.4.12
*/
module top();

bit [3:0] a;

bit [7:0] b = 8'b10101100;
bit [7:0] c = 8'b01010011;

initial begin
a = {b, c}[9:6];
end

endmodule
2 changes: 1 addition & 1 deletion third_party/cores/ariane
2 changes: 1 addition & 1 deletion third_party/cores/basejump_stl
Submodule basejump_stl updated 166 files
2 changes: 1 addition & 1 deletion third_party/cores/veer-el2
Submodule veer-el2 updated 52 files
+0 −44 .github/scripts/convert_coverage_data.sh
+0 −70 .github/scripts/gen_coverage_reports.sh
+0 −95 .github/scripts/update_webpage.sh
+2 −2 .github/workflows/build-verilator.yml
+6 −1 .github/workflows/ci.yml
+57 −0 .github/workflows/get-renode.yml
+16 −1 .github/workflows/gh-pages-pr-remove.yml
+24 −2 .github/workflows/publish-webpage.yml
+10 −2 .github/workflows/report-coverage.yml
+11 −5 .github/workflows/test-openocd.yml
+11 −5 .github/workflows/test-regression.yml
+26 −2 .github/workflows/test-renode.yml
+11 −5 .github/workflows/test-riscof.yml
+32 −133 .github/workflows/test-riscv-dv.yml
+12 −6 .github/workflows/test-uarch.yml
+2 −2 .github/workflows/test-uvm.yml
+12 −6 .github/workflows/test-verification.yml
+4 −4 design/dec/el2_dec_pmp_ctl.sv
+1 −1 design/el2_pmp.sv
+1 −2 docs/source/verification.md
+3 −3 testbench/ahb_sif.sv
+0 −2 testbench/openocd_scripts/jtag_cg.tcl
+1 −15 testbench/openocd_scripts/veer-el2-rst.cfg
+0 −3 testbench/openocd_scripts/verilator-rst.cfg
+54 −0 tools/SiteSpawner/.gitignore
+202 −0 tools/SiteSpawner/LICENSE
+85 −0 tools/SiteSpawner/README.md
+55 −0 tools/SiteSpawner/pyproject.toml
+334 −0 tools/SiteSpawner/src/sitespawner/__init__.py
+99 −0 tools/SiteSpawner/src/sitespawner/common.py
+50 −0 tools/SiteSpawner/src/sitespawner/convert_data.py
+241 −0 tools/SiteSpawner/src/sitespawner/gen_coverage_report.py
+114 −0 tools/SiteSpawner/src/sitespawner/generate.py
+366 −0 tools/SiteSpawner/src/sitespawner/genhtml.py
+33 −0 tools/SiteSpawner/src/sitespawner/update_style.py
+126 −0 tools/SiteSpawner/src/sitespawner/update_webpage.py
+22 −0 tools/SiteSpawner/styles/assets/chips-alliance-logo-mono.svg
+642 −0 tools/SiteSpawner/styles/cov.css
+20 −0 tools/SiteSpawner/styles/main.css
+75 −0 tools/SiteSpawner/template/coverage_report/coverage_report.html
+68 −0 tools/SiteSpawner/template/coverage_report/main_table.html
+75 −0 tools/SiteSpawner/template/coverage_report/src_view.html
+21 −0 tools/SiteSpawner/template/coverage_report/summary_table.html
+11 −0 tools/SiteSpawner/template/redirect.html
+93 −0 tools/SiteSpawner/template/webpage/conf.py
+24 −0 tools/SiteSpawner/template/webpage/coverage_dashboard.md
+13 −0 tools/SiteSpawner/template/webpage/dev.md
+8 −0 tools/SiteSpawner/template/webpage/index.md
+9 −0 tools/SiteSpawner/template/webpage/main.md
+0 −19 tools/renode/run-tests.sh
+0 −3 tools/riscv-dv/Makefile
+0 −4 tools/riscv-dv/README.md
2 changes: 1 addition & 1 deletion third_party/tools/circt-verilog
Submodule circt-verilog updated 218 files
1 change: 1 addition & 0 deletions third_party/tools/tree-sitter-systemverilog
2 changes: 1 addition & 1 deletion third_party/tools/verible
Submodule verible updated 29 files
+243 −94 .github/bin/run-clang-tidy-cached.cc
+13 −20 .github/workflows/verible-ci.yml
+1 −1 README.md
+2 −0 common/util/BUILD
+3 −1 common/util/tree_operations_test.cc
+1 −1 verilog/analysis/BUILD
+39 −1 verilog/analysis/checkers/BUILD
+3 −3 verilog/analysis/checkers/enum_name_style_rule.cc
+373 −0 verilog/analysis/checkers/explicit_begin_rule.cc
+94 −0 verilog/analysis/checkers/explicit_begin_rule.h
+492 −0 verilog/analysis/checkers/explicit_begin_rule_test.cc
+20 −12 verilog/analysis/checkers/instance_shadow_rule.cc
+3 −3 verilog/analysis/checkers/instance_shadow_rule.h
+14 −1 verilog/analysis/checkers/instance_shadow_rule_test.cc
+2 −2 verilog/analysis/checkers/package_filename_rule.cc
+154 −49 verilog/analysis/checkers/parameter_name_style_rule.cc
+25 −10 verilog/analysis/checkers/parameter_name_style_rule.h
+186 −0 verilog/analysis/checkers/parameter_name_style_rule_test.cc
+3 −3 verilog/analysis/checkers/signal_name_style_rule.cc
+304 −296 verilog/analysis/symbol_table.cc
+789 −594 verilog/analysis/symbol_table_test.cc
+3 −2 verilog/parser/verilog_parser_unittest.cc
+1 −0 verilog/tools/lint/BUILD
+2 −1 verilog/tools/lint/testdata/always_comb_blocking.sv
+2 −1 verilog/tools/lint/testdata/always_ff_non_blocking.sv
+4 −0 verilog/tools/lint/testdata/explicit_begin.sv
+3 −1 verilog/tools/lint/testdata/generate_begin_module.sv
+3 −1 verilog/tools/lint/testdata/plusarg_assignment.sv
+1 −0 verilog/tools/lint/testdata/suspicious_semicolon.sv
2 changes: 1 addition & 1 deletion third_party/tools/verilator
Submodule verilator updated 5446 files
2 changes: 1 addition & 1 deletion third_party/tools/yosys
Submodule yosys updated 125 files
11 changes: 10 additions & 1 deletion tools/runners.mk
Original file line number Diff line number Diff line change
Expand Up @@ -80,6 +80,15 @@ $(INSTALL_DIR)/lib/tree-sitter-verilog.so:
cd $(RDIR)/tree-sitter-verilog && npm install
/usr/bin/env python3 -c "from tree_sitter import Language; Language.build_library(\"$@\", [\"$(abspath $(RDIR)/tree-sitter-verilog)\"])"

# tree-sitter-systemverilog
tree-sitter-systemverilog: $(INSTALL_DIR)/lib/tree-sitter-systemverilog.so

$(INSTALL_DIR)/lib/tree-sitter-systemverilog.so:
mkdir -p $(INSTALL_DIR)/lib
cd $(RDIR)/tree-sitter-systemverilog && \
cc -fPIC -c -I. src/parser.c && \
cc -fPIC -shared *.o -o $@

# surelog-uhdm-verilator
verilator-uhdm: $(INSTALL_DIR)/bin/verilator-uhdm

Expand Down Expand Up @@ -173,6 +182,6 @@ $(INSTALL_DIR)/bin/circt-verilog:
ninja && ninja install

# setup the dependencies
RUNNERS_TARGETS := odin yosys icarus verilator slang zachjs-sv2v tree-sitter-verilog sv-parser moore verible surelog yosys-synlig verilator-uhdm circt-verilog
RUNNERS_TARGETS := odin yosys icarus verilator slang zachjs-sv2v tree-sitter-systemverilog tree-sitter-verilog sv-parser moore verible surelog yosys-synlig verilator-uhdm circt-verilog
.PHONY: $(RUNNERS_TARGETS)
runners: $(RUNNERS_TARGETS)
103 changes: 103 additions & 0 deletions tools/runners/tree_sitter_systemverilog.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,103 @@
#!/usr/bin/env python3
# -*- coding: utf-8 -*-
#
# Copyright (C) 2020 The SymbiFlow Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC

import os
import sys
import resource

from tree_sitter import Language, Parser
from BaseRunner import BaseRunner


class tree_sitter_systemverilog(BaseRunner):
libname = 'tree-sitter-systemverilog.so'
locpath = ['runners', 'lib', libname]
conpath = ['lib', libname]

def __init__(self):
super().__init__("tree-sitter-systemverilog", None, {"parsing"})

self.submodule = "third_party/tools/tree-sitter-systemverilog"
self.url = f"https://github.com/gmlarumbe/tree-sitter-systemverilog/tree/{self.get_commit()}"

def find_lib(self):
local_lib = ''
conda_lib = ''
try:
out = os.environ['OUT_DIR']
local_lib = os.path.abspath(os.path.join(out, *self.locpath))
except KeyError:
pass

try:
prefix = os.environ['CONDA_PREFIX']
conda_lib = os.path.abspath(os.path.join(prefix, *self.conpath))
except KeyError:
pass

return local_lib if os.path.isfile(local_lib) else conda_lib

def log_error(self, fname, row, col, err):
self.log += '{}:{}:{}: error: {}\n'.format(fname, row, col, err)

def walk(self, node, fname):
if not node.has_error:
return False

last_err = True

for child in node.children:
if self.walk(child, fname):
last_err = False

if last_err:
self.log_error(fname, *node.start_point, 'node type: ' + node.type)

return True

def run(self, tmp_dir, params):
self.ret = 0
self.log = ''

try:
lib = self.find_lib()

lang = Language(lib, 'verilog')

parser = Parser()
parser.set_language(lang)
except Exception as e:
self.log += f'{e}\n'
self.ret = 1

for src in params['files']:
f = None
try:
f = open(src, 'rb')
except IOError:
self.ret = 1
self.log_error(src, '', '', 'failed to open file')
continue

try:
tree = parser.parse(f.read())
if self.walk(tree.root_node, src):
self.ret = 1
except Exception as e:
self.log_error(src, '', '', 'unknown error: ' + str(e))
self.ret = 1
usage = resource.getrusage(resource.RUSAGE_SELF)
profiling_data = (usage.ru_utime, usage.ru_stime, usage.ru_maxrss)

return (self.log, self.ret) + profiling_data

def can_run(self):
return os.path.isfile(self.find_lib())

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