migrate I-extension opcodes

- the ordering in these files have changed to preserve the order in the latex- tables - also ecall and ebreak has been moved to rv_i instead of keeping them in 'systems' file.
borneoa · Apr 8, 2022 · b60b8e3 · b60b8e3
1 parent 75b28f2
commit b60b8e3
Show file tree

Hide file tree

Showing 3 changed files with 26 additions and 42 deletions.
diff --git a/rv32_i b/rv32_i
@@ -0,0 +1,4 @@
+$pseudo_op rv64_i::slli slli rd rs1 shamtw 31..25=0  14..12=1 6..2=0x04 1..0=3
+$pseudo_op rv64_i::srli srli rd rs1 shamtw 31..25=0  14..12=5 6..2=0x04 1..0=3
+$pseudo_op rv64_i::srai srai rd rs1 shamtw 31..25=32 14..12=5 6..2=0x04 1..0=3
+
diff --git a/opcodes-rv64i → rv64_i b/opcodes-rv64i → rv64_i
@@ -1,22 +1,17 @@
 # RV64I additions to RV32I
 
+lwu     rd rs1       imm12 14..12=6 6..2=0x00 1..0=3
+ld      rd rs1       imm12 14..12=3 6..2=0x00 1..0=3
+sd     imm12hi rs1 rs2 imm12lo 14..12=3 6..2=0x08 1..0=3
+slli    rd rs1 31..26=0  shamt 14..12=1 6..2=0x04 1..0=3
+srli    rd rs1 31..26=0  shamt 14..12=5 6..2=0x04 1..0=3
+srai    rd rs1 31..26=16 shamt 14..12=5 6..2=0x04 1..0=3
 addiw   rd rs1 imm12            14..12=0 6..2=0x06 1..0=3
 slliw   rd rs1 31..25=0  shamtw 14..12=1 6..2=0x06 1..0=3
 srliw   rd rs1 31..25=0  shamtw 14..12=5 6..2=0x06 1..0=3
 sraiw   rd rs1 31..25=32 shamtw 14..12=5 6..2=0x06 1..0=3
-
 addw    rd rs1 rs2 31..25=0  14..12=0 6..2=0x0E 1..0=3
 subw    rd rs1 rs2 31..25=32 14..12=0 6..2=0x0E 1..0=3
 sllw    rd rs1 rs2 31..25=0  14..12=1 6..2=0x0E 1..0=3
 srlw    rd rs1 rs2 31..25=0  14..12=5 6..2=0x0E 1..0=3
 sraw    rd rs1 rs2 31..25=32 14..12=5 6..2=0x0E 1..0=3
-
-ld      rd rs1       imm12 14..12=3 6..2=0x00 1..0=3
-lwu     rd rs1       imm12 14..12=6 6..2=0x00 1..0=3
-
-sd     imm12hi rs1 rs2 imm12lo 14..12=3 6..2=0x08 1..0=3
-
-# RV32 versions of these are in opcodes-pseudo
-slli    rd rs1 31..26=0  shamt 14..12=1 6..2=0x04 1..0=3
-srli    rd rs1 31..26=0  shamt 14..12=5 6..2=0x04 1..0=3
-srai    rd rs1 31..26=16 shamt 14..12=5 6..2=0x04 1..0=3
diff --git a/opcodes-rv32i → rv_i b/opcodes-rv32i → rv_i
@@ -1,33 +1,29 @@
-# format of a line in this file:
-# <instruction name> <args> <opcode>
-#
-# <opcode> is given by specifying one or more range/value pairs:
-# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0)
-#
-# <args> is one of rd, rs1, rs2, rs3, imm20, imm12, imm12lo, imm12hi,
-# shamtw, shamt, rm
+# rv_i
 
+lui     rd imm20 6..2=0x0D 1..0=3
+auipc   rd imm20 6..2=0x05 1..0=3
+jal     rd jimm20                          6..2=0x1b 1..0=3
+jalr    rd rs1 imm12              14..12=0 6..2=0x19 1..0=3
 beq     bimm12hi rs1 rs2 bimm12lo 14..12=0 6..2=0x18 1..0=3
 bne     bimm12hi rs1 rs2 bimm12lo 14..12=1 6..2=0x18 1..0=3
 blt     bimm12hi rs1 rs2 bimm12lo 14..12=4 6..2=0x18 1..0=3
 bge     bimm12hi rs1 rs2 bimm12lo 14..12=5 6..2=0x18 1..0=3
 bltu    bimm12hi rs1 rs2 bimm12lo 14..12=6 6..2=0x18 1..0=3
 bgeu    bimm12hi rs1 rs2 bimm12lo 14..12=7 6..2=0x18 1..0=3
-
-jalr    rd rs1 imm12              14..12=0 6..2=0x19 1..0=3
-
-jal     rd jimm20                          6..2=0x1b 1..0=3
-
-lui     rd imm20 6..2=0x0D 1..0=3
-auipc   rd imm20 6..2=0x05 1..0=3
-
+lb      rd rs1       imm12 14..12=0 6..2=0x00 1..0=3
+lh      rd rs1       imm12 14..12=1 6..2=0x00 1..0=3
+lw      rd rs1       imm12 14..12=2 6..2=0x00 1..0=3
+lbu     rd rs1       imm12 14..12=4 6..2=0x00 1..0=3
+lhu     rd rs1       imm12 14..12=5 6..2=0x00 1..0=3
+sb     imm12hi rs1 rs2 imm12lo 14..12=0 6..2=0x08 1..0=3
+sh     imm12hi rs1 rs2 imm12lo 14..12=1 6..2=0x08 1..0=3
+sw     imm12hi rs1 rs2 imm12lo 14..12=2 6..2=0x08 1..0=3
 addi    rd rs1 imm12           14..12=0 6..2=0x04 1..0=3
 slti    rd rs1 imm12           14..12=2 6..2=0x04 1..0=3
 sltiu   rd rs1 imm12           14..12=3 6..2=0x04 1..0=3
 xori    rd rs1 imm12           14..12=4 6..2=0x04 1..0=3
 ori     rd rs1 imm12           14..12=6 6..2=0x04 1..0=3
 andi    rd rs1 imm12           14..12=7 6..2=0x04 1..0=3
-
 add     rd rs1 rs2 31..25=0  14..12=0 6..2=0x0C 1..0=3
 sub     rd rs1 rs2 31..25=32 14..12=0 6..2=0x0C 1..0=3
 sll     rd rs1 rs2 31..25=0  14..12=1 6..2=0x0C 1..0=3
@@ -38,17 +34,6 @@ srl     rd rs1 rs2 31..25=0  14..12=5 6..2=0x0C 1..0=3
 sra     rd rs1 rs2 31..25=32 14..12=5 6..2=0x0C 1..0=3
 or      rd rs1 rs2 31..25=0  14..12=6 6..2=0x0C 1..0=3
 and     rd rs1 rs2 31..25=0  14..12=7 6..2=0x0C 1..0=3
-
-lb      rd rs1       imm12 14..12=0 6..2=0x00 1..0=3
-lh      rd rs1       imm12 14..12=1 6..2=0x00 1..0=3
-lw      rd rs1       imm12 14..12=2 6..2=0x00 1..0=3
-lbu     rd rs1       imm12 14..12=4 6..2=0x00 1..0=3
-lhu     rd rs1       imm12 14..12=5 6..2=0x00 1..0=3
-
-sb     imm12hi rs1 rs2 imm12lo 14..12=0 6..2=0x08 1..0=3
-sh     imm12hi rs1 rs2 imm12lo 14..12=1 6..2=0x08 1..0=3
-sw     imm12hi rs1 rs2 imm12lo 14..12=2 6..2=0x08 1..0=3
-
-fence       fm            pred succ     rs1 14..12=0 rd 6..2=0x03 1..0=3
-fence.i     imm12                       rs1 14..12=1 rd 6..2=0x03 1..0=3
-
+fence fm pred succ rs1 14..12=0 rd 6..2=0x03 1..0=3
+ecall    31..20=0x000 19..7=0 6..2=0x1C 1..0=3
+ebreak   31..20=0x001 19..7=0 6..2=0x1C 1..0=3