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Merge pull request riscv#276 from foss-for-synopsys-dwc-arc-processor…
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…s/UpdateDB

Move F extension CSRs to the rv_f
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@aswaterman
aswaterman authored Aug 22, 2024
2 parents 7206bf6 + 14c5be0 commit 41c6b4d
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Showing 2 changed files with 9 additions and 11 deletions.
9 changes: 9 additions & 0 deletions rv_f
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Original file line number Diff line number Diff line change
Expand Up @@ -29,3 +29,12 @@ fmv.w.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3
$pseudo_op rv_f::fmv.x.w fmv.x.s rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x14 1..0=3
$pseudo_op rv_f::fmv.w.x fmv.s.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3

#CSRs
$pseudo_op rv_zicsr::csrrs frflags rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3
$pseudo_op rv_zicsr::csrrw fsflags rd rs1 31..20=0x001 14..12=1 6..2=0x1C 1..0=3
$pseudo_op rv_zicsr::csrrwi fsflagsi rd zimm 31..20=0x001 14..12=5 6..2=0x1C 1..0=3
$pseudo_op rv_zicsr::csrrs frrm rd 19..15=0 31..20=0x002 14..12=2 6..2=0x1C 1..0=3
$pseudo_op rv_zicsr::csrrw fsrm rd rs1 31..20=0x002 14..12=1 6..2=0x1C 1..0=3
$pseudo_op rv_zicsr::csrrwi fsrmi rd zimm 31..20=0x002 14..12=5 6..2=0x1C 1..0=3
$pseudo_op rv_zicsr::csrrw fscsr rd rs1 31..20=0x003 14..12=1 6..2=0x1C 1..0=3
$pseudo_op rv_zicsr::csrrs frcsr rd 19..15=0 31..20=0x003 14..12=2 6..2=0x1C 1..0=3
11 changes: 0 additions & 11 deletions rv_zicsr
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Original file line number Diff line number Diff line change
Expand Up @@ -4,14 +4,3 @@ csrrc rd rs1 csr 14..12=3 6..2=0x1C 1..0=3
csrrwi rd csr zimm 14..12=5 6..2=0x1C 1..0=3
csrrsi rd csr zimm 14..12=6 6..2=0x1C 1..0=3
csrrci rd csr zimm 14..12=7 6..2=0x1C 1..0=3

$pseudo_op rv_zicsr::csrrs frflags rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3
$pseudo_op rv_zicsr::csrrw fsflags rd rs1 31..20=0x001 14..12=1 6..2=0x1C 1..0=3
$pseudo_op rv_zicsr::csrrwi fsflagsi rd zimm 31..20=0x001 14..12=5 6..2=0x1C 1..0=3
$pseudo_op rv_zicsr::csrrs frrm rd 19..15=0 31..20=0x002 14..12=2 6..2=0x1C 1..0=3
$pseudo_op rv_zicsr::csrrw fsrm rd rs1 31..20=0x002 14..12=1 6..2=0x1C 1..0=3
$pseudo_op rv_zicsr::csrrwi fsrmi rd zimm 31..20=0x002 14..12=5 6..2=0x1C 1..0=3
$pseudo_op rv_zicsr::csrrw fscsr rd rs1 31..20=0x003 14..12=1 6..2=0x1C 1..0=3
$pseudo_op rv_zicsr::csrrs frcsr rd 19..15=0 31..20=0x003 14..12=2 6..2=0x1C 1..0=3


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