Various FPU and warning fixes #427
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Signed-off-by: Paul Mackerras <[email protected]>
With ftdiv, we weren't setting result_exp to B.exponent before testing result_exp in state FTDIV_1; the fix is to transfer B.exponent to result_exp in state DO_FTDIV. With ftsqrt, we were setting bit 1 of the destination CR field to 0 always, due to a typo. Also move a couple of statements around to try to get slightly simpler logic. Signed-off-by: Paul Mackerras <[email protected]>
Signed-off-by: Paul Mackerras <[email protected]>
This fixes the following warning:
fetch1.vhdl:293:18:warning: declaration of "eaa_priv" hides signal "eaa_priv" [-Whide]
variable eaa_priv : std_ulogic;
^
In fact the signal "eaa_priv" is unused, so remove it.
Signed-off-by: Paul Mackerras <[email protected]>
This resolves various warnings and critical warnings from Vivado. In particular, the asynchronous loops in the xilinx hardware RNG were giving a lot of critical warnings, which proved to be difficult to suppress, so this instead makes all the xilinx platforms use the 'nonrandom.vhdl' implementation, which always returns an error. Signed-off-by: Paul Mackerras <[email protected]>
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