Efficient Multiple Constant Multiplication (MCM) Using DSP Blocks in Xilinx FPGAs

This work implements (with Python2) the technique proposed in paper "Efficient Multiple Constant Multiplication Using DSP Blocks in FPGA" presented in 2018 International Conference on Field-Programmable Logic and Applications (FPL).

Files

• generatemodule.py -- Includes functions for generating Verilog modules.

• mcm.py -- Includes functions for performing MCM on DSP blocks.

• main.py -- Top file.

If you use this work in your research/study, please cite our work:

@INPROCEEDINGS{8533518,
  author={A. C. {Mert} and H. {Azgin} and E. {Kalali} and I. {Hamzaoglu}},
  booktitle={2018 28th International Conference on Field Programmable Logic and Applications (FPL)}, 
  title={Efficient Multiple Constant Multiplication Using DSP Blocks in FPGA}, 
  year={2018},
  volume={},
  number={},
  pages={331-3313},}