write_verilog: emit $check cell names as labels

[rroohhh]

Right now assert/assume/cover cell labels get parsed as the cell name of the $check cell, but the verilog backend does not use that information again.

This now emits public names again as labels in the verilog backend.

Running the following script:

read -sv -formal <<EOF
module test();
    always test : assert(1);
endmodule
EOF
prep -top test
write_verilog

used to result in

(* keep =  1  *)
(* hdlname = "test" *)
(* top =  1  *)
(* src = "<<EOF:1.1-3.10" *)
module test();
  (* src = "<<EOF:2.9-2.25" *)
  wire test_EN;
  always @*
    if (1'h1) begin
      assert (1'h1);
    end
  assign test_EN = 1'h1;
endmodule

and with this change results in

(* keep =  1  *)
(* hdlname = "test" *)
(* top =  1  *)
(* src = "<<EOF:1.1-3.10" *)
module test();
  (* src = "<<EOF:2.9-2.25" *)
  wire test_EN;
  always @*
    if (1'h1) begin
      test: assert (1'h1);
    end
  assign test_EN = 1'h1;
endmodule

[whitequark]

LGTM!

[whitequark]

Let me know if you want a bump of amaranth-yosys with this commit included.