read_rtlil: Warn on assigns after switches in case rules

docs/source/appendix/rtlil_text.rst

@@ -242,15 +242,15 @@ Processes
 
 Declares a process, with zero or more attributes, with the given identifier in
 the enclosing module. The body of a process consists of zero or more
-assignments, exactly one switch, and zero or more syncs.
+assignments followed by zero or more switches and zero or more syncs.
 
 See :ref:`sec:rtlil_process` for an overview of processes.
 
 .. code:: BNF
 
     <process>       ::= <attr-stmt>* <proc-stmt> <process-body> <proc-end-stmt>
     <proc-stmt>     ::= process <id> <eol>
-    <process-body>  ::= <assign-stmt>* <switch>? <assign-stmt>* <sync>*
+    <process-body>  ::= <assign-stmt>* <switch>* <sync>*
     <assign-stmt>   ::= assign <dest-sigspec> <src-sigspec> <eol>
     <dest-sigspec>  ::= <sigspec>
     <src-sigspec>   ::= <sigspec>
@@ -262,8 +262,8 @@ Switches
 Switches test a signal for equality against a list of cases. Each case specifies
 a comma-separated list of signals to check against. If there are no signals in
 the list, then the case is the default case. The body of a case consists of zero
-or more switches and assignments. Both switches and cases may have zero or more
-attributes.
+or more assignments followed by zero or more switches. Both switches and cases
+may have zero or more attributes.
 
 .. code:: BNF
 
@@ -272,7 +272,7 @@ attributes.
     <case>              ::= <attr-stmt>* <case-stmt> <case-body>
     <case-stmt>         ::= case <compare>? <eol>
     <compare>           ::= <sigspec> (, <sigspec>)*
-    <case-body>         ::= (<switch> | <assign-stmt>)*
+    <case-body>         ::= <assign-stmt>* <switch>*
     <switch-end-stmt>   ::= end <eol>
 
 Syncs

frontends/rtlil/rtlil_frontend.cc

@@ -31,6 +31,11 @@ void rtlil_frontend_yyerror(char const *s)
 	YOSYS_NAMESPACE_PREFIX log_error("Parser error in line %d: %s\n", rtlil_frontend_yyget_lineno(), s);
 }
 
+void rtlil_frontend_yywarning(char const *s)
+{
+	YOSYS_NAMESPACE_PREFIX log_warning("In line %d: %s\n", rtlil_frontend_yyget_lineno(), s);
+}
+
 YOSYS_NAMESPACE_BEGIN
 
 struct RTLILFrontend : public Frontend {

frontends/rtlil/rtlil_frontend.h

@@ -42,6 +42,7 @@ YOSYS_NAMESPACE_END
 extern int rtlil_frontend_yydebug;
 int rtlil_frontend_yylex(void);
 void rtlil_frontend_yyerror(char const *s);
+void rtlil_frontend_yywarning(char const *s);
 void rtlil_frontend_yyrestart(FILE *f);
 int rtlil_frontend_yyparse(void);
 int rtlil_frontend_yylex_destroy(void);

frontends/rtlil/rtlil_parser.y

@@ -344,6 +344,16 @@ assign_stmt:
 	TOK_ASSIGN sigspec sigspec EOL {
 		if (attrbuf.size() != 0)
 			rtlil_frontend_yyerror("dangling attribute");
+
+		// See https://github.com/YosysHQ/yosys/pull/4765 for discussion on this
+		// warning
+		if (!switch_stack.back()->empty()) {
+			rtlil_frontend_yywarning(
+				"case rule assign statements after switch statements may cause unexpected behaviour. "
+				"The assign statement is reordered to come before all switch statements."
+			);
+		}
+
 		case_stack.back()->actions.push_back(RTLIL::SigSig(*$2, *$3));
 		delete $2;
 		delete $3;