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extract_fa: Fix xor3/xnor3 inversion bug #4691

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Feb 6, 2025
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5 changes: 3 additions & 2 deletions passes/techmap/extract_fa.cc
Original file line number Diff line number Diff line change
Expand Up @@ -412,14 +412,15 @@ struct ExtractFaWorker
facache[fakey] = make_tuple(X, Y, cell);
}

bool invert_y = f3i.inv_a ^ f3i.inv_b ^ f3i.inv_c;
if (func3.at(key).count(xor3_func)) {
SigBit YY = invert_xy ? module->NotGate(NEW_ID, Y) : Y;
SigBit YY = invert_xy ^ invert_y ? module->NotGate(NEW_ID, Y) : Y;
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@povik povik Feb 6, 2025

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This makes sense: at this point we are looking to implement xor3, respectively xnor3 in terms of the signals held in A, B, C.

Y is the Y output of a (possibly cached) full-adder cell over A, B, C, with inversions inserted as indicated by f3i.inv_a/b/c, with the added caveat that if invert_xy is true, all of the inputs are complemented on top of that.

With that being said the logic around here seems correct to decide whether we need to use Y, or Y complemented to get the xor3/xnor3 result.

for (auto bit : func3.at(key).at(xor3_func))
assign_new_driver(bit, YY);
}

if (func3.at(key).count(xnor3_func)) {
SigBit YY = invert_xy ? Y : module->NotGate(NEW_ID, Y);
SigBit YY = invert_xy ^ invert_y ? Y : module->NotGate(NEW_ID, Y);
for (auto bit : func3.at(key).at(xnor3_func))
assign_new_driver(bit, YY);
}
Expand Down
29 changes: 29 additions & 0 deletions tests/various/bug3879.ys
Original file line number Diff line number Diff line change
@@ -0,0 +1,29 @@
read_verilog <<EOF
module gcd(I, D);

output [2:0] I;
input [3:0] D;

assign I = D[0]+D[1]+D[2]+D[3];
endmodule
EOF
design -save input

prep

design -stash gold

design -load input

synth -top gcd -flatten

extract_fa -v

design -stash gate

design -copy-from gold -as gold gcd
design -copy-from gate -as gate gcd

miter -equiv -make_assert -flatten gold gate miter

sat -verify -prove-asserts -show-all miter
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