attempting to sim split memory tests

and failing
YosysHQ · Dec 1, 2023 · 5634d98 · 5634d98
1 parent d9d54e6
commit 5634d98
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Showing 2 changed files with 57 additions and 14 deletions.
diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py
@@ -113,6 +113,7 @@
 EOF
 read_verilog -defer -formal mem_tb.v
 chparam{param_str} -set VECTORLEN {vectorlen} TB
+read_verilog +/quicklogic/qlf_k6n10f/cells_sim.v
 hierarchy -top TB -check
 proc
 sim -clock clk -n {vectorlen} -assert
@@ -184,6 +185,28 @@
 );\
 """
 
+double_sync_ram_sdp_submodule = """\
+double_sync_ram_sdp #(\\
+	.ADDRESS_WIDTH_A(ADDRESS_WIDTH_A),\\
+	.DATA_WIDTH_A(DATA_WIDTH_A),\\
+	.ADDRESS_WIDTH_B(ADDRESS_WIDTH_B),\\
+	.DATA_WIDTH_B(DATA_WIDTH_B)\\
+) uut (\\
+	.clk_a(clk),\\
+	.write_enable_a(wce_a),\\
+	.address_in_w_a(wa_a),\\
+	.address_in_r_a(ra_a),\\
+	.data_in_a(wd_a),\\
+	.data_out_b(rq_b),\\
+	.clk_b(clk),\\
+	.write_enable_b(wce_b),\\
+	.address_in_w_b(wa_b),\\
+	.address_in_r_b(ra_b),\\
+	.data_in_b(wd_b),\\
+	.data_out_b(rq_b)\\
+);\
+"""
+
 @dataclass
 class TestClass:
     params: dict[str, int]
@@ -334,6 +357,20 @@ class TestClass:
             {"rq_a": 0xdeadbeef},
         ]
     ),
+    TestClass( # basic split SDP test
+        params={"ADDRESS_WIDTH_A": 10, "DATA_WIDTH_A": 16,
+                "ADDRESS_WIDTH_B": 10, "DATA_WIDTH_B": 16},
+        top="double_sync_ram_sdp",
+        assertions=[],
+        test_steps=[
+            {"wce_a": 1, "wa_a": 0x0A,      "wce_b": 1, "wa_b": 0xBA,
+            "wd_a": 0x1234,                 "wd_b": 0x4567},
+            {"wce_a": 1, "wa_a": 0xFF,      "wce_b": 1, "wa_b": 0x0A,
+            "wd_a": 0,                      "wd_b": 0xbeef},
+            {"rce_a": 1, "ra_a": 0x0A,      "rce_b": 1, "ra_b": 0x0A},
+            {"rq_a": 0x1234,                "rq_b": 0xbeef},
+        ]
+    ),
 ]
 
 for (params, top, assertions) in blockram_tests:
@@ -396,6 +433,8 @@ class TestClass:
                 uut_submodule = sync_ram_sdp_wwr_submodule
             elif top == "sync_ram_sdp_wrr":
                 uut_submodule = sync_ram_sdp_wrr_submodule
+            elif top == "double_sync_ram_sdp":
+                uut_submodule = double_sync_ram_sdp_submodule
             else:
                 raise NotImplementedError(f"missing submodule header for {top}")
             mem_test_vector = ""

diff --git a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v
@@ -1,26 +1,30 @@
 module TB(input clk);
 
 parameter ADDRESS_WIDTH = 10;
+parameter ADDRESS_WIDTH_A = ADDRESS_WIDTH;
+parameter ADDRESS_WIDTH_B = ADDRESS_WIDTH;
 parameter DATA_WIDTH = 36;
+parameter DATA_WIDTH_A = DATA_WIDTH;
+parameter DATA_WIDTH_B = DATA_WIDTH;
 parameter VECTORLEN = 16;
 parameter SHIFT_VAL = 0;
 localparam MAX_WIDTH = 36;
 
 reg rce_a_testvector [VECTORLEN-1:0];
-reg [ADDRESS_WIDTH-1:0] ra_a_testvector [VECTORLEN-1:0];
+reg [ADDRESS_WIDTH_A-1:0] ra_a_testvector [VECTORLEN-1:0];
 reg [MAX_WIDTH-1:0] rq_a_expected [VECTORLEN-1:0];
 
 reg wce_a_testvector [VECTORLEN-1:0];
-reg [ADDRESS_WIDTH-1:0] wa_a_testvector [VECTORLEN-1:0];
-reg [DATA_WIDTH-1:0] wd_a_testvector [VECTORLEN-1:0];
+reg [ADDRESS_WIDTH_A-1:0] wa_a_testvector [VECTORLEN-1:0];
+reg [DATA_WIDTH_A-1:0] wd_a_testvector [VECTORLEN-1:0];
 
 reg rce_b_testvector [VECTORLEN-1:0];
-reg [ADDRESS_WIDTH-1:0] ra_b_testvector [VECTORLEN-1:0];
+reg [ADDRESS_WIDTH_B-1:0] ra_b_testvector [VECTORLEN-1:0];
 reg [MAX_WIDTH-1:0] rq_b_expected [VECTORLEN-1:0];
 
 reg wce_b_testvector [VECTORLEN-1:0];
-reg [ADDRESS_WIDTH-1:0] wa_b_testvector [VECTORLEN-1:0];
-reg [DATA_WIDTH-1:0] wd_b_testvector [VECTORLEN-1:0];
+reg [ADDRESS_WIDTH_B-1:0] wa_b_testvector [VECTORLEN-1:0];
+reg [DATA_WIDTH_B-1:0] wd_b_testvector [VECTORLEN-1:0];
 
 reg [$clog2(VECTORLEN)-1:0] i = 0;
 
@@ -44,22 +48,22 @@ end
 
 
 wire rce_a = rce_a_testvector[i];
-wire [ADDRESS_WIDTH-1:0] ra_a = ra_a_testvector[i];
+wire [ADDRESS_WIDTH_A-1:0] ra_a = ra_a_testvector[i];
 wire [MAX_WIDTH-1:0] rq_a_e = rq_a_expected[i];
-wire [DATA_WIDTH-1:0] rq_a;
+wire [DATA_WIDTH_A-1:0] rq_a;
 
 wire wce_a = wce_a_testvector[i];
-wire [ADDRESS_WIDTH-1:0] wa_a = wa_a_testvector[i];
-wire [DATA_WIDTH-1:0] wd_a = wd_a_testvector[i];
+wire [ADDRESS_WIDTH_A-1:0] wa_a = wa_a_testvector[i];
+wire [DATA_WIDTH_A-1:0] wd_a = wd_a_testvector[i];
 
 wire rce_b = rce_b_testvector[i];
-wire [ADDRESS_WIDTH-1:0] ra_b = ra_b_testvector[i];
+wire [ADDRESS_WIDTH_B-1:0] ra_b = ra_b_testvector[i];
 wire [MAX_WIDTH-1:0] rq_b_e = rq_b_expected[i];
-wire [DATA_WIDTH-1:0] rq_b;
+wire [DATA_WIDTH_B-1:0] rq_b;
 
 wire wce_b = wce_b_testvector[i];
-wire [ADDRESS_WIDTH-1:0] wa_b = wa_b_testvector[i];
-wire [DATA_WIDTH-1:0] wd_b = wd_b_testvector[i];
+wire [ADDRESS_WIDTH_B-1:0] wa_b = wa_b_testvector[i];
+wire [DATA_WIDTH_B-1:0] wd_b = wd_b_testvector[i];
 
 `UUT_SUBMODULE