Add left and right bound properties to wire. Add some tests

frontends/verific/verific.cc

@@ -450,8 +450,30 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
 		auto type_range = nl->GetTypeRange(obj->Name());
 		if (!type_range)
 			return;
+		if (type_range->IsTypeScalar()) {
+		  const long long left_bound = type_range->GetScalarRangeLeftBound();
+		  const long long right_bound = type_range->GetScalarRangeRightBound();
+		  const unsigned bit_width = type_range->NumElements();
+
+		  const std::bitset<sizeof(long long) * CHAR_BIT> binary_left(left_bound);
+		  log_assert(bit_width <= binary_left.size());
+		  std::vector<bool> bits_left(bit_width);
+		  for (size_t i = 0; i < bit_width; ++i) {
+		    bits_left[i] = binary_left[i];
+		  }
+
+		  const std::bitset<sizeof(long long) * CHAR_BIT> binary_right(right_bound);
+		  log_assert(bit_width <= binary_right.size());
+		  std::vector<bool> bits_right(bit_width);
+		  for (size_t i = 0; i < bit_width; ++i) {
+		    bits_right[i] = binary_right[i];
+		  }
+
+		  attributes.emplace(ID(left_bound), RTLIL::Const(bits_left));
+		  attributes.emplace(ID(right_bound), RTLIL::Const(bits_right));
+		}
 		if (!type_range->IsTypeEnum())
-			return;
+		  return;
 #ifdef VERIFIC_VHDL_SUPPORT
 		if (nl->IsFromVhdl() && strcmp(type_range->GetTypeName(), "STD_LOGIC") == 0)
 			return;

tests/verific/large_integer_range.vhdl

@@ -0,0 +1,20 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity work is
+  Port (
+    -- 32 bit range is -2,147,483,648 to 2,147,483,647
+    -- 64 bit range is -9,223,372,036,854,775,808 to 9,223,372,036,854,775,807
+    a : in INTEGER range -4 to 10147483749;
+    b : out INTEGER range -4 to 10147483748
+    );
+end entity work;
+
+architecture Behavioral of work is
+begin
+  process(a)
+  begin
+    b <= a;
+  end process;
+end architecture Behavioral;

tests/verific/large_integer_range.ys

@@ -0,0 +1,2 @@
+verific -vhdl2019 large_integer_range.vhdl
+verific -import work

tests/verific/negative_integer_range.vhdl

@@ -0,0 +1,18 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity work is
+    Port (
+        a : in INTEGER range -10 to 15;
+        b : out INTEGER range -9 to 15
+    );
+end entity work;
+
+architecture Behavioral of work is
+begin
+    process(a)
+    begin
+        b <= a;
+    end process;
+end architecture Behavioral;

tests/verific/negative_integer_range.ys

@@ -0,0 +1,2 @@
+verific -vhdl2019 negative_integer_range.vhdl
+verific -import work

tests/verific/positive_integer_range.vhdl

@@ -0,0 +1,18 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity work is
+    Port (
+        a : in INTEGER range 1 to 15;
+        b : out INTEGER range 2 to 15
+    );
+end entity work;
+
+architecture Behavioral of work is
+begin
+    process(a)
+    begin
+        b <= a;
+    end process;
+end architecture Behavioral;

tests/verific/positive_integer_range.ys

@@ -0,0 +1,2 @@
+verific -vhdl2019 positive_integer_range.vhdl
+verific -import work

tests/verific/zero_to_positive_integer_range.vhdl

@@ -0,0 +1,18 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity work is
+    Port (
+        a : in INTEGER range 0 to 15;
+        b : out INTEGER range 1 to 15
+    );
+end entity work;
+
+architecture Behavioral of work is
+begin
+    process(a)
+    begin
+        b <= a;
+    end process;
+end architecture Behavioral;

tests/verific/zero_to_positive_integer_range.ys

@@ -0,0 +1,2 @@
+verific -vhdl2019 zero_to_positive_integer_range.vhdl
+verific -import work