Merge branches 'feature/TinyUSB-improvements' and 'feature/gd32f4' of…

… github.com:WootingKb/tinyusb into feature/gd32f4

src/common/tusb_mcu.h

@@ -245,6 +245,10 @@
 #elif TU_CHECK_MCU(OPT_MCU_GD32F303)
   #define TUP_DCD_ENDPOINT_MAX  8
 
+#elif TU_CHECK_MCU(OPT_MCU_GD32F4)
+  #define TUP_USBIP_DWC2
+  // USBHS has max 6, is max 4 for USBFS
+  #define TUP_DCD_ENDPOINT_MAX  6
 //------------- Broadcom -------------//
 #elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837)
   #define TUP_USBIP_DWC2

src/device/dcd.h

@@ -132,6 +132,9 @@ void dcd_connect(uint8_t rhport) TU_ATTR_WEAK;
 // Disconnect by disabling internal pull-up resistor on D+/D-
 void dcd_disconnect(uint8_t rhport) TU_ATTR_WEAK;
 
+// Set new (max) intended bus speed
+void dcd_speed_set(tusb_speed_t speed) TU_ATTR_WEAK;
+
 //--------------------------------------------------------------------+
 // Endpoint API
 //--------------------------------------------------------------------+

src/device/usbd.c

@@ -334,6 +334,15 @@ tusb_speed_t tud_speed_get(void)
   return (tusb_speed_t) _usbd_dev.speed;
 }
 
+bool tud_speed_set(tusb_speed_t speed)
+{
+  TU_VERIFY(dcd_speed_set);
+
+  dcd_speed_set(speed);
+
+  return true;
+}
+
 bool tud_connected(void)
 {
   return _usbd_dev.connected;

src/device/usbd.h

@@ -65,6 +65,10 @@ extern void dcd_int_handler(uint8_t rhport);
 // Get current bus speed
 tusb_speed_t tud_speed_get(void);
 
+// Set new (max) intended bus speed
+// Return false if not supported
+bool tud_speed_set(tusb_speed_t speed);
+
 // Check if device is connected (may not mounted/configured yet)
 // True if just got out of Bus Reset and received the very first data from host
 bool tud_connected(void);

src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h

@@ -61,7 +61,7 @@
   // F1 names this differently from the rest
   #define USB_CNTR_LPMODE   USB_CNTR_LP_MODE
 
-#elif defined(GD32F3_FSDEV)
+#elif CFG_TUSB_MCU == OPT_MCU_GD32F303
   #include "gd32_fsdev_common.h"
   #define PMA_LENGTH (512u)
   // NO internal Pull-ups

src/portable/synopsys/dwc2/dcd_dwc2.c

@@ -40,6 +40,8 @@
   #include "dwc2_esp32.h"
 #elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
   #include "dwc2_gd32.h"
+#elif TU_CHECK_MCU(OPT_MCU_GD32F4)
+  #include "dwc2_gd32f.h"
 #elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837)
   #include "dwc2_bcm.h"
 #elif TU_CHECK_MCU(OPT_MCU_EFM32GG)
@@ -93,6 +95,25 @@ static uint16_t ep0_pending[2];                   // Index determines direction
 static uint16_t _allocated_fifo_words_tx;         // TX FIFO size in words (IN EPs)
 static bool     _out_ep_closed;                   // Flag to check if RX FIFO size needs an update (reduce its size)
 
+static tusb_speed_t _usb_max_speed = TUSB_SPEED_INVALID;  // Value to indicate the intended (max) USB speed
+
+// Flush the TX-FIFO and wait until we have confirmed it cleared
+static void dcd_flush_tx_endpoint(dwc2_regs_t * dwc2, uint8_t epnum)
+{
+  dwc2->grstctl |= GRSTCTL_TXFNUM_Msk & (epnum << GRSTCTL_TXFNUM_Pos);
+  dwc2->grstctl |= GRSTCTL_TXFFLSH;
+
+  while (0 != (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk)) { ; }
+}
+
+// Flush the RX-FIFO and wait until we have confirmed it cleared
+static void dcd_flush_rx_endpoint(dwc2_regs_t * dwc2)
+{
+  dwc2->grstctl |= GRSTCTL_RXFFLSH;
+
+  while (0 != (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk)) { ; }
+}
+
 // Calculate the RX FIFO size according to recommendations from reference manual
 static inline uint16_t calc_rx_ff_size(uint16_t ep_size)
 {
@@ -123,6 +144,12 @@ static void bus_reset(uint8_t rhport)
 
   dwc2_regs_t * dwc2 = DWC2_REG(rhport);
 
+  // Flush receiving FIFO for all OUT endpoints
+//  dcd_flush_rx_endpoint(dwc2);
+
+  // Flush transmit FIFOs for all IN endpoints
+  dcd_flush_tx_endpoint(dwc2, 0x10U);
+
   tu_memclr(xfer_status, sizeof(xfer_status));
   _out_ep_closed = false;
 
@@ -353,12 +380,35 @@ static void reset_core(dwc2_regs_t * dwc2)
   while ( !(dwc2->grstctl & GRSTCTL_AHBIDL) ) { }
 
   // wait for device mode ?
+
+  // Flush receiving FIFO for all OUT endpoints
+  dcd_flush_rx_endpoint(dwc2);
+
+  // Flush transmit FIFOs for all IN endpoints
+  dcd_flush_tx_endpoint(dwc2, 0x10U);
+}
+
+static uint32_t get_hs_phy_type(dwc2_regs_t * dwc2) {
+  #if TU_CHECK_MCU(OPT_MCU_GD32F4)
+
+    #if defined(USE_ULPI_PHY)
+      return HS_PHY_TYPE_ULPI;
+    #elif defined(USE_EMBEDDED_PHY)
+      // TODO: Is this correct?
+      return HS_PHY_TYPE_NONE;
+    #else
+      #error "Unsupported PHY option"
+    #endif
+
+  #else
+    return dwc2->ghwcfg2_bm.hs_phy_type;
+  #endif
 }
 
 static bool phy_hs_supported(dwc2_regs_t * dwc2)
 {
   // note: esp32 incorrect report its hs_phy_type as utmi
-  return TUD_OPT_HIGH_SPEED && dwc2->ghwcfg2_bm.hs_phy_type != HS_PHY_TYPE_NONE;
+  return TUD_OPT_HIGH_SPEED && get_hs_phy_type(dwc2) != HS_PHY_TYPE_NONE;
 }
 
 static void phy_fs_init(dwc2_regs_t * dwc2)
@@ -393,7 +443,7 @@ static void phy_hs_init(dwc2_regs_t * dwc2)
   // De-select FS PHY
   gusbcfg &= ~GUSBCFG_PHYSEL;
 
-  if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI)
+  if (get_hs_phy_type(dwc2) == HS_PHY_TYPE_ULPI)
   {
     TU_LOG(DWC2_DEBUG, "Highspeed ULPI PHY init\r\n");
 
@@ -423,7 +473,7 @@ static void phy_hs_init(dwc2_regs_t * dwc2)
   dwc2->gusbcfg = gusbcfg;
 
   // mcu specific phy init
-  dwc2_phy_init(dwc2, dwc2->ghwcfg2_bm.hs_phy_type);
+  dwc2_phy_init(dwc2, get_hs_phy_type(dwc2));
 
   // Reset core after selecting PHY
   reset_core(dwc2);
@@ -432,20 +482,37 @@ static void phy_hs_init(dwc2_regs_t * dwc2)
   // - 9 if using 8-bit PHY interface
   // - 5 if using 16-bit PHY interface
   gusbcfg &= ~GUSBCFG_TRDT_Msk;
+  #ifdef USE_ULPI_PHY
+  gusbcfg |= (9u) << GUSBCFG_TRDT_Pos;
+  #else
   gusbcfg |= (dwc2->ghwcfg4_bm.utmi_phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
+  #endif
   dwc2->gusbcfg = gusbcfg;
 
   // MCU specific PHY update post reset
-  dwc2_phy_update(dwc2, dwc2->ghwcfg2_bm.hs_phy_type);
+  dwc2_phy_update(dwc2, get_hs_phy_type(dwc2));
 
   // Set max speed
   uint32_t dcfg = dwc2->dcfg;
   dcfg &= ~DCFG_DSPD_Msk;
-  dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos;
+
+  // Handle the intended (max) speed
+  switch (_usb_max_speed)
+  {
+    // Limit to Full-Speed
+    case TUSB_SPEED_FULL:
+      dcfg |= DCFG_DSPD_FS_HSPHY << DCFG_DSPD_Pos;
+    break;
+
+    // Default to Hi-Speed if speed is not Full-Speed
+    default:
+      dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos;
+    break;
+  }
 
   // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required
   // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347)
-  if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) dcfg |= DCFG_XCVRDLY;
+  if (get_hs_phy_type(dwc2)== HS_PHY_TYPE_ULPI) dcfg |= DCFG_XCVRDLY;
 
   dwc2->dcfg = dcfg;
 }
@@ -457,7 +524,7 @@ static bool check_dwc2(dwc2_regs_t * dwc2)
 #endif
 
   // For some reasons: GD32VF103 snpsid and all hwcfg register are always zero (skip it)
-#if !TU_CHECK_MCU(OPT_MCU_GD32VF103)
+#if !TU_CHECK_MCU(OPT_MCU_GD32VF103, OPT_MCU_GD32F4)
   uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK;
   TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID);
 #endif
@@ -629,6 +696,10 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
                                   (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) |
                                   (xfer->max_size << DOEPCTL_MPSIZ_Pos);
 
+    // Flush receiving FIFO for all OUT endpoints
+    // ToDo: Is that needed???
+//    dcd_flush_rx_endpoint(dwc2);
+
     dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum);
   }
   else
@@ -671,6 +742,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
                                  (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) |
                                  (xfer->max_size << DIEPCTL_MPSIZ_Pos);
 
+    // Flush transmit FIFOs for the IN endpoint
+    dcd_flush_tx_endpoint(dwc2, epnum);
+
     dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum));
   }
 
@@ -796,9 +870,12 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
     }
 
     // Flush the FIFO, and wait until we have confirmed it cleared.
-    dwc2->grstctl |= (epnum << GRSTCTL_TXFNUM_Pos);
+/*    dwc2->grstctl |= (epnum << GRSTCTL_TXFNUM_Pos);
     dwc2->grstctl |= GRSTCTL_TXFFLSH;
     while ( (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) != 0 ) {}
+*/
+    // Flush transmit FIFOs for the IN endpoint
+    dcd_flush_tx_endpoint(dwc2, epnum);
   }
   else
   {
@@ -1304,4 +1381,9 @@ void dcd_int_handler(uint8_t rhport)
   //  }
 }
 
+void dcd_speed_set(tusb_speed_t speed)
+{
+  _usb_max_speed = speed;
+}
+
 #endif

src/portable/synopsys/dwc2/dwc2_gd32f.h

@@ -0,0 +1,144 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _DWC2_GD32F_H_
+#define _DWC2_GD32F_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// EP_MAX       : Max number of bi-directional endpoints including EP0
+// EP_FIFO_SIZE : Size of dedicated USB SRAM
+#if CFG_TUSB_MCU == OPT_MCU_GD32F4
+#include "gd32f4xx.h"
+#define EP_MAX_FS 4
+#define EP_FIFO_SIZE_FS 1280U
+#define EP_MAX_HS 6
+#define EP_FIFO_SIZE_HS 4096U
+
+#else
+#error "Unsupported MCUs"
+#endif
+
+// On GD32 we associate Port0 to OTG_FS, and Port1 to OTG_HS
+#if TUD_OPT_RHPORT == 0
+#define DWC2_REG_BASE USBFS_BASE
+#define DWC2_EP_MAX EP_MAX_FS
+#define DWC2_EP_FIFO_SIZE EP_FIFO_SIZE_FS
+#define RHPORT_IRQn USBFS_IRQn
+
+#else
+#define DWC2_REG_BASE USBHS_BASE
+#define DWC2_EP_MAX EP_MAX_HS
+#define DWC2_EP_FIFO_SIZE EP_FIFO_SIZE_HS
+#define RHPORT_IRQn USBHS_IRQn
+
+#endif
+
+extern uint32_t SystemCoreClock;
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_dcd_int_enable(uint8_t rhport) {
+  (void)rhport;
+  NVIC_EnableIRQ(RHPORT_IRQn);
+  // NVIC_EnableIRQ(USBHS_WKUP_IRQn);
+}
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_dcd_int_disable(uint8_t rhport) {
+  (void)rhport;
+  NVIC_DisableIRQ(RHPORT_IRQn);
+  // NVIC_DisableIRQ(USBHS_WKUP_IRQn);
+}
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_remote_wakeup_delay(void) {
+  // try to delay for 1 ms
+  uint32_t count = SystemCoreClock / 1000;
+  while (count--)
+    __NOP();
+}
+
+// MCU specific PHY init, called BEFORE core reset
+static inline void dwc2_phy_init(dwc2_regs_t *dwc2, uint8_t hs_phy_type) {
+
+  if (hs_phy_type == HS_PHY_TYPE_NONE) {
+    // Enable on-chip FS PHY
+    dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
+    dwc2->gusbcfg |= GUSBCFG_PHYSEL;
+    // TODO: Put under a define?
+    // Disable VBUS sensing
+    dwc2->stm32_gccfg |= STM32_GCCFG_VBDEN;
+
+  } else {
+    // Disable FS PHY
+    dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
+    dwc2->gusbcfg &= ~GUSBCFG_PHYSEL;
+  }
+}
+
+// MCU specific PHY update, it is called AFTER init() and core reset
+static inline void dwc2_phy_update(dwc2_regs_t *dwc2, uint8_t hs_phy_type) {
+  // used to set turnaround time for fullspeed, nothing to do in highspeed mode
+  // if (hs_phy_type == HS_PHY_TYPE_NONE) {
+  //   // Turnaround timeout depends on the AHB clock dictated by STM32
+  //   Reference
+  //   // Manual
+  //   uint32_t turnaround;
+
+  //   if (SystemCoreClock >= 32000000u)
+  //     turnaround = 0x6u;
+  //   else if (SystemCoreClock >= 27500000u)
+  //     turnaround = 0x7u;
+  //   else if (SystemCoreClock >= 24000000u)
+  //     turnaround = 0x8u;
+  //   else if (SystemCoreClock >= 21800000u)
+  //     turnaround = 0x9u;
+  //   else if (SystemCoreClock >= 200000000u)
+  //     turnaround = 0xAu;
+  //   else if (SystemCoreClock >= 18500000u)
+  //     turnaround = 0xBu;
+  //   else if (SystemCoreClock >= 17200000u)
+  //     turnaround = 0xCu;
+  //   else if (SystemCoreClock >= 16000000u)
+  //     turnaround = 0xDu;
+  //   else if (SystemCoreClock >= 15000000u)
+  //     turnaround = 0xEu;
+  //   else
+  //     turnaround = 0xFu;
+
+  //   dwc2->gusbcfg =
+  //       (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (turnaround <<
+  //       GUSBCFG_TRDT_Pos);
+  // }
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DWC2_GD32F_H_ */