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Fixed SPI for sync implementation #28

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Fixed SPI for sync implementation #28

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2 changes: 1 addition & 1 deletion Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@ defmt-rtt = "0.3.0"
panic-semihosting = "0.6"

[dev-dependencies.stm32f4xx-hal]
version = "0.13.2"
version = "0.14.0"
features = ["stm32f411"]

[features]
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4 changes: 2 additions & 2 deletions examples/rtic.rs
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Expand Up @@ -14,8 +14,8 @@ mod app {
timer::delay::Delay,
};

type Scl = Pin<Alternate<OpenDrain, 4>, 'B', 6>;
type Sda = Pin<Alternate<OpenDrain, 4>, 'B', 7>;
type Scl = Pin<'B', 6, Alternate<4, OpenDrain>>;
type Sda = Pin<'B', 7, Alternate<4, OpenDrain>>;

#[shared]
struct Shared {}
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11 changes: 7 additions & 4 deletions src/spi.rs
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Expand Up @@ -5,7 +5,7 @@ use core::future::Future;
#[cfg(feature = "sync")]
use embedded_hal::delay::blocking::DelayUs;
#[cfg(feature = "sync")]
use embedded_hal::spi::blocking::{SpiBus, SpiDevice};
use embedded_hal::spi::blocking::{SpiBus, SpiBusRead, SpiBusWrite, SpiDevice};
#[cfg(feature = "async")]
use embedded_hal_async::delay::DelayUs as AsyncDelayUs;
#[cfg(feature = "async")]
Expand Down Expand Up @@ -157,9 +157,9 @@ where

fn write_register(&mut self, register: u8, payload: u8) -> Result<(), Error<Self::Error>> {
// If the first bit is 0, the register is written.
let transfer = [register & 0x7f, payload];
let data = [register & 0x7f, payload];
self.spi
.transfer(&mut [], &transfer)
.write(&data)
.map_err(|e| Error::Bus(SPIError::SPI(e)))?;
Ok(())
}
Expand Down Expand Up @@ -256,7 +256,10 @@ where
data: &mut [u8],
) -> Result<(), Error<SPIError<SPI::Error>>> {
self.spi
.transfer(data, &[register])
.transaction(|bus| {
bus.write(&[register])?;
bus.read(data)
})
.await
.map_err(|e| Error::Bus(SPIError::SPI(e)))?;
Ok(())
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