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Please help me approve this pull request! Thank you :) #234

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merged 3 commits into from
Oct 15, 2024

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elliesara
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I wasn't able to pass the case sensitivity check for some reason, but all other tests passed.

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Thank you for your pull request! 👋

@elliesara elliesara changed the title Please help me approve this pull request! Please help me approve this pull request! Thank you :) Oct 14, 2024
@lukasc-ubc
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Error: layout does not have 1 top cell. It has 2.

@lukasc-ubc
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We are now past the deadline.

Our next submission will be in February 2025.
The repository will be set up soon: https://github.com/SiEPIC/openEBL-2025-02

You may fix your design and submit next time.

thank you
Lukas

@lukasc-ubc lukasc-ubc closed this Oct 15, 2024
@lukasc-ubc lukasc-ubc reopened this Oct 15, 2024
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Welcome, new contributor!

Thank you for uploading your design.

If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V).

Please note that we have added a new rule (on May 2, 2024) to SiEPIC-Tools and the EBeam PDK, so please make sure your tools are running the latest version. The rule is: The grating coupler spacing (pitch) must be at least 60.0 microns. This is to help avoid the probe station from accidentally aligning to an adjacent circuit.

You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline.

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Thank you for your pull request! 👋

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Welcome, new contributor!

Thank you for uploading your design.

If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V).

Please note that we have added a new rule (on May 2, 2024) to SiEPIC-Tools and the EBeam PDK, so please make sure your tools are running the latest version. The rule is: The grating coupler spacing (pitch) must be at least 60.0 microns. This is to help avoid the probe station from accidentally aligning to an adjacent circuit.

You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline.

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Thank you for your pull request! 👋

@lukasc-ubc lukasc-ubc merged commit a619b92 into SiEPIC:main Oct 15, 2024
2 of 3 checks passed
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2 participants