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Xinliu0260 patch 1 #9755

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拉取/合并请求描述:(PR description)

[

为什么提交这份PR (why to submit this PR)

stm32h7系列开启DCache后,使用串口设备框架V2进行串口DMA接收发送

  • 接收数据时,现有版本对接收FIFO的buffer进行了Cache无效化,但会连带无效化接收FIFO结构体中的其他成员数据,导致接收FIFO结构体其他成员数据出错,比如对buffer地址、大小、读写索引的初始化没被写入到内存,对Buffer的操作仍需依赖这些成员信息,最终造成总线错误类型的硬件错误中断等
  • 发送数据与内存数据不一致,需要在DMA发送前,对发送FIFO的buffer进行清空Cache

你的解决方案是什么 (what is your solution)

  • 串口设备驱动框架层中的.h文件定义struct rt_serial_rx_fifo和struct rt_serial_tx_fifo时,对buffer成员进行32字节地址对齐约束
struct rt_serial_rx_fifo
{
    ......
    rt_align(32) rt_uint8_t buffer[];
};

struct rt_serial_tx_fifo
{
    .....
    rt_align(32) rt_uint8_t buffer[];
};
  • stm32h7串口设备驱动层在发送前,Clean DCache
static rt_ssize_t stm32_transmit(struct rt_serial_device     *serial,
                                       rt_uint8_t           *buf,
                                       rt_size_t             size,
                                       rt_uint32_t           tx_flag)
{
.......
    if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
    {
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
        struct rt_serial_tx_fifo *tx_fifo = (struct rt_serial_tx_fifo *) serial->serial_tx;
        SCB_CleanDCache_by_Addr((uint32_t *)tx_fifo->rb.buffer_ptr, tx_fifo->rb.buffer_size);
#endif        
        HAL_UART_Transmit_DMA(&uart->handle, buf, size);
        return size;
    }
......
}

请提供验证的bsp和config (provide the config and bsp)

  • BSP: bsp\stm32\stm32h743-atk-apollo
  • .config:
    CONFIG_BSP_SCB_ENABLE_I_CACHE=y
    CONFIG_BSP_SCB_ENABLE_D_CACHE=y
    CONFIG_RT_USING_SERIAL_V2=y
    CONFIG_RT_SERIAL_USING_DMA=y
    CONFIG_BSP_USING_UART2=y
    CONFIG_BSP_UART2_RX_BUFSIZE=256
    CONFIG_BSP_UART2_TX_BUFSIZE=256
    CONFIG_BSP_UART2_RX_USING_DMA=y
    CONFIG_BSP_UART2_TX_USING_DMA=y
  • action:
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]

当前拉取/合并请求的状态 Intent for your PR

必须选择一项 Choose one (Mandatory):

  • 本拉取/合并请求是一个草稿版本 This PR is for a code-review and is intended to get feedback
  • 本拉取/合并请求是一个成熟版本 This PR is mature, and ready to be integrated into the repo

代码质量 Code Quality:

我在这个拉取/合并请求中已经考虑了 As part of this pull request, I've considered the following:

  • 已经仔细查看过代码改动的对比 Already check the difference between PR and old code
  • 代码风格正确,包括缩进空格,命名及其他风格 Style guide is adhered to, including spacing, naming and other styles
  • 没有垃圾代码,代码尽量精简,不包含#if 0代码,不包含已经被注释了的代码 All redundant code is removed and cleaned up
  • 所有变更均有原因及合理的,并且不会影响到其他软件组件代码或BSP All modifications are justified and not affect other components or BSP
  • 对难懂代码均提供对应的注释 I've commented appropriately where code is tricky
  • 代码是高质量的 Code in this PR is of high quality
  • 已经使用formatting 等源码格式化工具确保格式符合RT-Thread代码规范 This PR complies with RT-Thread code specification
  • 如果是新增bsp, 已经添加ci检查到.github/workflows/bsp_buildings.yml 详细请参考链接BSP自查

修复stm32h7开启DCache之后,串口dma发送数据不同步的bug
对上次提交的增补,对rt_serial_tx_fifo中的buffer成员约束32字节地址对齐;
另外修复串口DMA接收,buffer因为不是32字节地址对齐,在SCB_InvalidateDCache_by_Addr时导致rt_serial_rx_fifo结构体中的其他成员数据被Invalidate,未同步写入到memory中的初始化数据被修改,最终造成总线错误,MCU卡死
@CLAassistant
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CLAassistant commented Dec 8, 2024

CLA assistant check
All committers have signed the CLA.

@BernardXiong
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请给出正确的标题。如这个PR和issue关联,请在内容中进行关联

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3 participants