first commit: Version 0.2.0

.gitignore

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+*.pyc
+*.out
+parsetab.py

LICENSE.txt

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+Apache License 2.0
+(http://www.apache.org/licenses/LICENSE-2.0)

MANIFEST.in

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+include README.md
+include README.rst
+include LICENSE.txt
+include Makefile
+include default.config
+include base.mk
+include mem-incr.hex
+recursive-include include *
+recursive-include c_lib *
+recursive-include examples *
+recursive-include tests *

Makefile

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+TARGET=./tests/memcpy/
+
+.PHONY: all
+all: sim
+
+.PHONY: build
+build:
+	make build -C $(TARGET)
+
+.PHONY: sim
+sim:
+	make sim -C $(TARGET)
+
+.PHONY: vcs_sim
+vcs_sim:
+	make vcs_sim -C $(TARGET)
+
+.PHONY: view
+view:
+	make view -C $(TARGET)
+
+.PHONY: clean
+clean:
+	make clean -C ipgen
+	make clean -C ./examples
+	make clean -C ./tests
+	rm -rf *.pyc __pycache__ ipgen.egg-info build dist
+
+.PHONY: release
+release:
+	pandoc README.md -t rst > README.rst

README.md

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+IPgen
+==============================
+
+IP-core package generator for AXI4/Avalon
+
+Copyright (C) 2015, Shinya Takamaeda-Yamazaki
+
+E-mail: shinya\_at\_is.naist.jp
+
+
+License
+==============================
+
+Apache License 2.0
+(http://www.apache.org/licenses/LICENSE-2.0)
+
+
+What's IPgen?
+==============================
+
+IPgen is a lightweight IP-core package synthesizer from abstract RTL sources.
+You can implement both AXI4 and Avalon IP-core by using the provided abstract interfaces.
+
+- ipgen_master_memory:  memory-mapped access interface (master)
+- ipgen_slave_memory:   memory-mapped access interface (slave)
+- ipgen_master_lite_memory:  memory-mapped access lite interface (master)
+- ipgen_slave_lite_memory:   memory-mapped access lite interface (slave)
+
+
+Installation
+==============================
+
+Requirements
+--------------------
+
+- Python: 2.7, 3.4 or later
+
+Python3 is recommended.
+
+- Icarus Verilog: 0.9.7 or later
+
+Install on your platform. For exmple, on Ubuntu:
+
+    sudo apt-get install iverilog
+
+- Jinja2: 2.8 or later
+- pytest: 2.8.2 or later
+- pytest-pythonpath: 0.7 or later
+
+Install on your python environment by using pip.
+
+    pip install jinja2 pytest pytest-pythonpath
+
+- Pyverilog: 1.0.0 or later
+
+Install from pip:
+
+    pip install pyverilog
+
+Install
+--------------------
+
+Install IPgen.
+
+    python setup.py install
+
+
+Getting Started
+==============================
+
+You can use the ipgen command from your console.
+
+    ipgen
+
+You can find the sample projects in 'tests/memcpy.v'.
+
+- userlogic.v  : User-defined Verilog code using IPgen abstract memory interfaces
+
+Then type 'make' and 'make run' to simulate sample system.
+
+    make build
+    make sim
+
+Or type commands as below directly.
+
+    ipgen default.config -t userlogic -I include tests/memcpyuserlogic.v
+    iverilog -I ipen_userlogic_v1_00_a/hdl/verilog/ ipgen_userlogic_v1_00_a/test/test_ipgen_userlogic.v 
+    ./a.out
+
+IPgen compiler generates a directory for IP-core (ipgen\_userlogic\_v1\_00\_a, in this example).
+
+'ipgen\_userlogic\_v1\_00\_a.v' includes 
+- IP-core RTL design (hdl/verilog/ipgen\_userlogic.v)
+- Test bench (test/test\_ipgen\_userlogic.v) 
+- XPS setting files (ipgen\_userlogic\_v2\_1\_0.{mpd,pao,tcl})
+- IP-XACT file (component.xml)
+
+A bit-stream can be synthesized by using Xilinx Platform Studio, Xilinx Vivado, and Altera Qsys.
+In case of XPS, please copy the generated IP-core into 'pcores' directory of XPS project.
+
+
+IPgen Command Options
+==============================
+
+Command
+------------------------------
+
+    ipgen [config] [-t topmodule] [-I includepath]+ [--memimg=filename] [--usertest=filename] [file]+
+
+Description
+------------------------------
+
+* file
+    - User-logic Verilog file (.v) and FPGA system memory specification (.config).
+      Automatically, .v file is recognized as a user-logic Verilog file, and 
+      .config file recongnized as a memory specification of used FPGA system, respectively.
+* config
+    - Configuration file which includes memory and device specification 
+* -t
+    - Name of user-defined top module, default is "userlogic".
+* -I
+    - Include path for input Verilog HDL files.
+* --memimg
+    - DRAM image file in HEX DRAM (option, if you need).
+      The file is copied into test directory.
+      If no file is assigned, the array is initialized with incremental values.
+* --usertest
+    - User-defined test code file (option, if you need).
+      The code is copied into testbench script.
+
+
+Related Project
+==============================
+
+[Pyverilog](http://shtaxxx.github.io/Pyverilog/)
+- Python-based Hardware Design Processing Toolkit for Verilog HDL
+- Used as basic code analyser and generator
+

README.rst

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+IPgen
+=====
+
+IP-core package generator for AXI4/Avalon
+
+Copyright (C) 2015, Shinya Takamaeda-Yamazaki
+
+E-mail: shinya\_at\_is.naist.jp
+
+License
+=======
+
+Apache License 2.0 (http://www.apache.org/licenses/LICENSE-2.0)
+
+What's IPgen?
+=============
+
+IPgen is a lightweight IP-core package synthesizer from abstract RTL
+sources. You can implement both AXI4 and Avalon IP-core by using the
+provided abstract interfaces.
+
+-  ipgen\_master\_memory: memory-mapped access interface (master)
+-  ipgen\_slave\_memory: memory-mapped access interface (slave)
+-  ipgen\_master\_lite\_memory: memory-mapped access lite interface
+   (master)
+-  ipgen\_slave\_lite\_memory: memory-mapped access lite interface
+   (slave)
+
+Installation
+============
+
+Requirements
+------------
+
+-  Python: 2.7, 3.4 or later
+
+Python3 is recommended.
+
+-  Icarus Verilog: 0.9.7 or later
+
+Install on your platform. For exmple, on Ubuntu:
+
+::
+
+    sudo apt-get install iverilog
+
+-  Jinja2: 2.8 or later
+-  pytest: 2.8.2 or later
+-  pytest-pythonpath: 0.7 or later
+
+Install on your python environment by using pip.
+
+::
+
+    pip install jinja2 pytest pytest-pythonpath
+
+-  Pyverilog: 1.0.0 or later
+
+Install from pip:
+
+::
+
+    pip install pyverilog
+
+Install
+-------
+
+Install IPgen.
+
+::
+
+    python setup.py install
+
+Getting Started
+===============
+
+You can use the ipgen command from your console.
+
+::
+
+    ipgen
+
+You can find the sample projects in 'tests/memcpy.v'.
+
+-  userlogic.v : User-defined Verilog code using IPgen abstract memory
+   interfaces
+
+Then type 'make' and 'make run' to simulate sample system.
+
+::
+
+    make build
+    make sim
+
+Or type commands as below directly.
+
+::
+
+    ipgen default.config -t userlogic -I include tests/memcpyuserlogic.v
+    iverilog -I ipen_userlogic_v1_00_a/hdl/verilog/ ipgen_userlogic_v1_00_a/test/test_ipgen_userlogic.v 
+    ./a.out
+
+IPgen compiler generates a directory for IP-core
+(ipgen\_userlogic\_v1\_00\_a, in this example).
+
+'ipgen\_userlogic\_v1\_00\_a.v' includes - IP-core RTL design
+(hdl/verilog/ipgen\_userlogic.v) - Test bench
+(test/test\_ipgen\_userlogic.v) - XPS setting files
+(ipgen\_userlogic\_v2\_1\_0.{mpd,pao,tcl}) - IP-XACT file
+(component.xml)
+
+A bit-stream can be synthesized by using Xilinx Platform Studio, Xilinx
+Vivado, and Altera Qsys. In case of XPS, please copy the generated
+IP-core into 'pcores' directory of XPS project.
+
+IPgen Command Options
+=====================
+
+Command
+-------
+
+::
+
+    ipgen [config] [-t topmodule] [-I includepath]+ [--memimg=filename] [--usertest=filename] [file]+
+
+Description
+-----------
+
+-  file
+
+   -  User-logic Verilog file (.v) and FPGA system memory specification
+      (.config). Automatically, .v file is recognized as a user-logic
+      Verilog file, and .config file recongnized as a memory
+      specification of used FPGA system, respectively.
+
+-  config
+
+   -  Configuration file which includes memory and device specification
+
+-  -t
+
+   -  Name of user-defined top module, default is "userlogic".
+
+-  -I
+
+   -  Include path for input Verilog HDL files.
+
+-  --memimg
+
+   -  DRAM image file in HEX DRAM (option, if you need). The file is
+      copied into test directory. If no file is assigned, the array is
+      initialized with incremental values.
+
+-  --usertest
+
+   -  User-defined test code file (option, if you need). The code is
+      copied into testbench script.
+
+Related Project
+===============
+
+`Pyverilog <http://shtaxxx.github.io/Pyverilog/>`__ - Python-based
+Hardware Design Processing Toolkit for Verilog HDL - Used as basic code
+analyser and generator