Add support for STM32H755/CM4

PyCubed-Mini · Jun 13, 2024 · d00a5b2 · d00a5b2
1 parent d030c34
commit d00a5b2
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Showing 10 changed files with 230 additions and 16 deletions.
diff --git a/ports/stm/Makefile b/ports/stm/Makefile
@@ -61,35 +61,44 @@ CFLAGS += -Wno-undef -Wno-shadow -Wno-cast-align $(ADD_CFLAGS)
 CFLAGS += -mthumb -mabi=aapcs-linux
 
 # Arm core selection
-MCU_FLAGS_L4 = -mcpu=cortex-m4
-MCU_FLAGS_F4 = -mcpu=cortex-m4
-MCU_FLAGS_F7 = -mcpu=cortex-m7
-MCU_FLAGS_H7 = -mcpu=cortex-m7
+ARM_CORTEX_L4 = m4
+ARM_CORTEX_F4 = m4
+ARM_CORTEX_F7 = m7
+ARM_CORTEX_H7 = m7
 
 ifeq ($(MCU_VARIANT),$(filter $(MCU_VARIANT),STM32H755xx))
 	ifeq ($(MCU_CORE), $(filter $(MCU_CORE),CM4))
-		MCU_FLAGS_H7 = -mcpu=cortex-m4 -DCORE_CM4
+		ARM_CORTEX_H7 = m4
+		CFLAGS += -DCORE_CM4
 	else ifeq ($(MCU_CORE), $(filter $(MCU_CORE),CM7))
-		MCU_FLAGS_H7 = -mcpu=cortex-m7 -DCORE_CM7
+		ARM_CORTEX_H7 = m7
+		CFLAGS += -DCORE_CM7
 	else
 		$(error MCU_CORE must be set to CM4 or CM7 for dual-core processors)
 	endif
 endif
 
-CFLAGS += $(MCU_FLAGS_$(MCU_SERIES))
+CFLAGS += -mcpu=cortex-$(ARM_CORTEX_$(MCU_SERIES))
 
 # Select HAL file for distribution via mpconfigport
 CFLAGS += -DSTM32_HAL_H="<stm32$(MCU_SERIES_LOWER)xx_hal.h>"
 
 CFLAGS += -DSTM32_SERIES_LOWER='"stm32$(MCU_SERIES_LOWER)"'
 
 # Floating point settings
-ifeq ($(MCU_VARIANT),$(filter $(MCU_VARIANT),STM32F765xx STM32F767xx STM32F769xx STM32H743xx STM32H755xx))
+ifeq ($(ARM_CORTEX_$(MCU_SERIES)),$(filter $(ARM_CORTEX_$(MCU_SERIES)),m7))
 CFLAGS += -mfpu=fpv5-d16 -mfloat-abi=hard
 else
 CFLAGS += -mfpu=fpv4-sp-d16 -mfloat-abi=hard
 endif
 
+# TCM settings
+ifeq ($(ARM_CORTEX_$(MCU_SERIES)),$(filter $(ARM_CORTEX_$(MCU_SERIES)),m7))
+CFLAGS += -DCPY_TCM=1
+else
+CFLAGS += -DCPY_TCM=0
+endif
+
 # Need both command and valid file to use uf2 bootloader
 ifndef LD_FILE
     ifneq ($(and $(UF2_BOOTLOADER),$(LD_BOOT)),)

diff --git a/ports/stm/boards/STM32H755_cm4_fs.ld b/ports/stm/boards/STM32H755_cm4_fs.ld
@@ -0,0 +1,40 @@
+/*
+    GNU linker script for STM32H755 with filesystem, tcm
+    CM4 (second core) at 0x08100000 - 0x081FFFFF
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+_ld_default_stack_size = 24K;
+
+/* Specify the memory areas */
+MEMORY
+{
+    FLASH (rx)          : ORIGIN = 0x08100000, LENGTH = 1024K
+    FLASH_ISR (rx)      : ORIGIN = 0x08100000, LENGTH = 128K    /* sector 0, 128K */
+    FLASH_FS (r)        : ORIGIN = 0x08120000, LENGTH = 384K    /* sector 1-3, 128K */
+    FLASH_FIRMWARE (rx) : ORIGIN = 0x08180000, LENGTH = 512K    /* sectors 4*128 */
+    DTCM (xrw)          : ORIGIN = 0x20000000, LENGTH = 128K
+    RAM_D1 (xrw)        : ORIGIN = 0x24000000, LENGTH = 512K    /* AXI SRAM */
+    SRAM_D2 (xrw)       : ORIGIN = 0x30000000, LENGTH = 288K    /* AHB D2 SRAM */
+    RAM (xrw)           : ORIGIN = 0x10000000, LENGTH = 288K    /* Use SRAM 2 for CM4 */
+    SRAM_D3 (xrw)       : ORIGIN = 0x38000000, LENGTH = 64K     /* AHB D3 SRAM */
+    ITCM (xrw)          : ORIGIN = 0x00000000, LENGTH = 64K
+}
+
+/* produce a link error if there is not this amount of RAM for these sections */
+_minimum_stack_size = 24K; /*TODO: this can probably be bigger, but how big?*/
+_minimum_heap_size = 16K;
+
+/* brainless copy paste for stack code. Results in ambiguous hard crash */
+/* _ld_default_stack_size = 20K; */
+
+/* Define the top end of the stack.  The stack is full descending so begins just
+   above last byte of RAM.  Note that EABI requires the stack to be 8-byte
+   aligned for a call. */
+_estack = ORIGIN(RAM) + LENGTH(RAM);
+
+/* RAM extents for the garbage collector */
+_ram_start = ORIGIN(RAM);
+_ram_end = ORIGIN(RAM) + LENGTH(RAM);
diff --git a/ports/stm/boards/STM32H755_cm7_fs.ld b/ports/stm/boards/STM32H755_cm7_fs.ld
@@ -1,5 +1,6 @@
 /*
     GNU linker script for STM32H755 with filesystem, tcm
+    CM7 (first core) at 0x08000000 - 0x080FFFFF
 */
 
 /* Entry Point */
@@ -16,8 +17,8 @@ MEMORY
     FLASH_FIRMWARE (rx) : ORIGIN = 0x08080000, LENGTH = 512K    /* sectors 4*128 */
     DTCM (xrw)          : ORIGIN = 0x20000000, LENGTH = 128K
     RAM (xrw)           : ORIGIN = 0x24000000, LENGTH = 512K    /* AXI SRAM */
-    SRAM_D2 (xrw)       : ORIGIN = 0x30000000, LENGTH = 288K    /* AHB1 SRAM */
-    SRAM_D3 (xrw)       : ORIGIN = 0x30040000, LENGTH = 64K     /* AHB2 SRAM */
+    SRAM_D2 (xrw)       : ORIGIN = 0x30000000, LENGTH = 288K    /* AHB D2 SRAM */
+    SRAM_D3 (xrw)       : ORIGIN = 0x38000000, LENGTH = 64K     /* AHB D3 SRAM */
     ITCM (xrw)          : ORIGIN = 0x00000000, LENGTH = 64K
 }
 
@@ -28,8 +29,8 @@ _minimum_heap_size = 16K;
 /* brainless copy paste for stack code. Results in ambiguous hard crash */
 /* _ld_default_stack_size = 20K; */
 
-/* Define tho top end of the stack.  The stack is full descending so begins just
-   above last byte of RAM.  Note that EABI requires the stack to be 8-byte
+/* Define the top end of the stack.  The stack is full descending so begins just
+   above last byte of the DTCM.  Note that EABI requires the stack to be 8-byte
    aligned for a call. */
 _estack = ORIGIN(DTCM) + LENGTH(DTCM);
 

diff --git a/ports/stm/boards/nucleo_h755zi_cm4/board.c b/ports/stm/boards/nucleo_h755zi_cm4/board.c
@@ -0,0 +1,9 @@
+// This file is part of the CircuitPython project: https://circuitpython.org
+//
+// SPDX-FileCopyrightText: Copyright (c) 2024 Scott Shawcroft for Adafruit Industries
+//
+// SPDX-License-Identifier: MIT
+
+#include "supervisor/board.h"
+
+// Use the MP_WEAK supervisor/shared/board.c versions of routines not defined here.
diff --git a/ports/stm/boards/nucleo_h755zi_cm4/mpconfigboard.h b/ports/stm/boards/nucleo_h755zi_cm4/mpconfigboard.h
@@ -0,0 +1,27 @@
+// This file is part of the CircuitPython project: https://circuitpython.org
+//
+// SPDX-FileCopyrightText: Copyright (c) 2024 Lucian Copeland for Adafruit Industries
+//
+// SPDX-License-Identifier: MIT
+
+#pragma once
+
+// Micropython setup
+
+#define MICROPY_HW_BOARD_NAME       "NUCLEO STM32H755 (CM4)"
+#define MICROPY_HW_MCU_NAME         "STM32H755"
+
+#define FLASH_PAGE_SIZE             (0x4000)
+
+#define HSE_VALUE                   ((uint32_t)8000000)
+#define LSE_VALUE                   ((uint32_t)32768)
+#define BOARD_HSE_SOURCE            (RCC_HSE_BYPASS) // ST boards use the STLink clock signal
+#define BOARD_HAS_LOW_SPEED_CRYSTAL (1)
+#define BOARD_POWER_SUPPLY          (PWR_DIRECT_SMPS_SUPPLY) // Nucleo-H755ZI-Q uses an SMPS by default
+#define CPY_CLK_VSCALE              (PWR_REGULATOR_VOLTAGE_SCALE2)
+// Running core clock at 240 MHz (instead of maximum 480 MHz) due to power supply
+// CM4 core is after CPY_CLK_AHBDIV, so CM4 frequency is 120 MHz
+#define CPY_CLK_PLLN                (240) 
+
+#define CIRCUITPY_CONSOLE_UART_RX (&pin_PD09)
+#define CIRCUITPY_CONSOLE_UART_TX (&pin_PD08)
diff --git a/ports/stm/boards/nucleo_h755zi_cm4/mpconfigboard.mk b/ports/stm/boards/nucleo_h755zi_cm4/mpconfigboard.mk
@@ -0,0 +1,18 @@
+USB_VID = 0x239A
+USB_PID = 0x809C
+USB_PRODUCT = "Nucleo H755ZI CM4 - CPy"
+USB_MANUFACTURER = "STMicroelectronics"
+
+INTERNAL_FLASH_FILESYSTEM = 1
+
+MCU_SERIES = H7
+MCU_VARIANT = STM32H755xx
+MCU_PACKAGE = LQFP144
+MCU_CORE = CM4
+
+LD_COMMON = boards/common_default.ld
+LD_FILE = boards/STM32H755_cm4_fs.ld
+
+CIRCUITPY_BLEIO = 0
+CIRCUITPY_BLEIO_HCI = 0
+CIRCUITPY_BLE_FILE_SERVICE = 0
diff --git a/ports/stm/boards/nucleo_h755zi_cm4/pins.c b/ports/stm/boards/nucleo_h755zi_cm4/pins.c
@@ -0,0 +1,106 @@
+// This file is part of the CircuitPython project: https://circuitpython.org
+//
+// SPDX-FileCopyrightText: Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
+//
+// SPDX-License-Identifier: MIT
+
+#include "shared-bindings/board/__init__.h"
+
+static const mp_rom_map_elem_t board_module_globals_table[] = {
+    CIRCUITPYTHON_BOARD_DICT_STANDARD_ITEMS
+
+    { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA03) },
+    { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PC00) },
+    { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) },
+    { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PB01) },
+    { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PC02) },
+    { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PF10) },
+    { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PF04) },
+    { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PF05) },
+    { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PF06) },
+    { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PB07) },
+    { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PB06) },
+    { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PG14) },
+    { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PE13) },
+    { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PE14) },
+    { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PE11) },
+    { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PE09) },
+    { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PG12) },
+    { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PF03) },
+    { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PD15) },
+    { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PD14) },
+    { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PB05) },
+    { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_PC06) },
+    { MP_ROM_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_PB15) },
+    { MP_ROM_QSTR(MP_QSTR_D18), MP_ROM_PTR(&pin_PB13) },
+    { MP_ROM_QSTR(MP_QSTR_D19), MP_ROM_PTR(&pin_PB12) },
+    { MP_ROM_QSTR(MP_QSTR_D20), MP_ROM_PTR(&pin_PA15) },
+    { MP_ROM_QSTR(MP_QSTR_D21), MP_ROM_PTR(&pin_PC07) },
+    { MP_ROM_QSTR(MP_QSTR_D22), MP_ROM_PTR(&pin_PB05) },
+    { MP_ROM_QSTR(MP_QSTR_D23), MP_ROM_PTR(&pin_PB03) },
+    { MP_ROM_QSTR(MP_QSTR_D24), MP_ROM_PTR(&pin_PA04) },
+    { MP_ROM_QSTR(MP_QSTR_D25), MP_ROM_PTR(&pin_PB04) },
+    { MP_ROM_QSTR(MP_QSTR_D26), MP_ROM_PTR(&pin_PG06) },
+    { MP_ROM_QSTR(MP_QSTR_D27), MP_ROM_PTR(&pin_PB02) },
+    { MP_ROM_QSTR(MP_QSTR_D28), MP_ROM_PTR(&pin_PD13) },
+    { MP_ROM_QSTR(MP_QSTR_D29), MP_ROM_PTR(&pin_PD12) },
+    { MP_ROM_QSTR(MP_QSTR_D30), MP_ROM_PTR(&pin_PD11) },
+    { MP_ROM_QSTR(MP_QSTR_D31), MP_ROM_PTR(&pin_PE02) },
+    { MP_ROM_QSTR(MP_QSTR_D32), MP_ROM_PTR(&pin_PA00) },
+    { MP_ROM_QSTR(MP_QSTR_D33), MP_ROM_PTR(&pin_PB00) },
+    { MP_ROM_QSTR(MP_QSTR_D34), MP_ROM_PTR(&pin_PE00) },
+    { MP_ROM_QSTR(MP_QSTR_D35), MP_ROM_PTR(&pin_PB11) },
+    { MP_ROM_QSTR(MP_QSTR_D36), MP_ROM_PTR(&pin_PB10) },
+    { MP_ROM_QSTR(MP_QSTR_D37), MP_ROM_PTR(&pin_PE15) },
+    { MP_ROM_QSTR(MP_QSTR_D38), MP_ROM_PTR(&pin_PE06) },
+    { MP_ROM_QSTR(MP_QSTR_D39), MP_ROM_PTR(&pin_PE12) },
+    { MP_ROM_QSTR(MP_QSTR_D40), MP_ROM_PTR(&pin_PE10) },
+    { MP_ROM_QSTR(MP_QSTR_D41), MP_ROM_PTR(&pin_PE07) },
+    { MP_ROM_QSTR(MP_QSTR_D42), MP_ROM_PTR(&pin_PE08) },
+    { MP_ROM_QSTR(MP_QSTR_D43), MP_ROM_PTR(&pin_PC08) },
+    { MP_ROM_QSTR(MP_QSTR_D44), MP_ROM_PTR(&pin_PC09) },
+    { MP_ROM_QSTR(MP_QSTR_D45), MP_ROM_PTR(&pin_PC10) },
+    { MP_ROM_QSTR(MP_QSTR_D46), MP_ROM_PTR(&pin_PC11) },
+    { MP_ROM_QSTR(MP_QSTR_D47), MP_ROM_PTR(&pin_PC12) },
+    { MP_ROM_QSTR(MP_QSTR_D48), MP_ROM_PTR(&pin_PD02) },
+    { MP_ROM_QSTR(MP_QSTR_D49), MP_ROM_PTR(&pin_PG02) },
+    { MP_ROM_QSTR(MP_QSTR_D50), MP_ROM_PTR(&pin_PG03) },
+    { MP_ROM_QSTR(MP_QSTR_D51), MP_ROM_PTR(&pin_PD07) },
+    { MP_ROM_QSTR(MP_QSTR_D52), MP_ROM_PTR(&pin_PD06) },
+    { MP_ROM_QSTR(MP_QSTR_D53), MP_ROM_PTR(&pin_PD05) },
+    { MP_ROM_QSTR(MP_QSTR_D54), MP_ROM_PTR(&pin_PD04) },
+    { MP_ROM_QSTR(MP_QSTR_D55), MP_ROM_PTR(&pin_PD03) },
+    { MP_ROM_QSTR(MP_QSTR_D56), MP_ROM_PTR(&pin_PE02) },
+    { MP_ROM_QSTR(MP_QSTR_D57), MP_ROM_PTR(&pin_PE04) },
+    { MP_ROM_QSTR(MP_QSTR_D58), MP_ROM_PTR(&pin_PE05) },
+    { MP_ROM_QSTR(MP_QSTR_D59), MP_ROM_PTR(&pin_PE06) },
+    { MP_ROM_QSTR(MP_QSTR_D60), MP_ROM_PTR(&pin_PE03) },
+    { MP_ROM_QSTR(MP_QSTR_D61), MP_ROM_PTR(&pin_PF08) },
+    { MP_ROM_QSTR(MP_QSTR_D62), MP_ROM_PTR(&pin_PF07) },
+    { MP_ROM_QSTR(MP_QSTR_D63), MP_ROM_PTR(&pin_PF09) },
+    { MP_ROM_QSTR(MP_QSTR_D64), MP_ROM_PTR(&pin_PG01) },
+    { MP_ROM_QSTR(MP_QSTR_D65), MP_ROM_PTR(&pin_PG00) },
+    { MP_ROM_QSTR(MP_QSTR_D66), MP_ROM_PTR(&pin_PD01) },
+    { MP_ROM_QSTR(MP_QSTR_D67), MP_ROM_PTR(&pin_PD00) },
+    { MP_ROM_QSTR(MP_QSTR_D68), MP_ROM_PTR(&pin_PF00) },
+    { MP_ROM_QSTR(MP_QSTR_D69), MP_ROM_PTR(&pin_PF01) },
+    { MP_ROM_QSTR(MP_QSTR_D70), MP_ROM_PTR(&pin_PF02) },
+    { MP_ROM_QSTR(MP_QSTR_D71), MP_ROM_PTR(&pin_PE00) },
+    { MP_ROM_QSTR(MP_QSTR_D72), MP_ROM_PTR(&pin_PB02) },
+    { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB09) },
+    { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB08) },
+    { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB05) },
+    { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PA06) },
+    { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PA05) },
+    { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PB07) },
+    { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PB06) },
+    { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PB00) },
+    { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PE01) },
+    { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PB14) },
+    { MP_ROM_QSTR(MP_QSTR_SW), MP_ROM_PTR(&pin_PC13) },
+};
+MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table);
diff --git a/ports/stm/peripherals/rtc.c b/ports/stm/peripherals/rtc.c
@@ -269,7 +269,11 @@ void RTC_WKUP_IRQHandler(void) {
         wkup_callback();
     }
     __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF);
+    #if defined(DUAL_CORE) && defined(CORE_CM4)
+    __HAL_RTC_WAKEUPTIMER_EXTID2_CLEAR_FLAG();
+    #else
     __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
+    #endif
     hrtc.State = HAL_RTC_STATE_READY;
 }
 

diff --git a/ports/stm/supervisor/port.c b/ports/stm/supervisor/port.c
@@ -42,7 +42,7 @@
 
 void NVIC_SystemReset(void) NORETURN;
 
-#if (CPY_STM32H7) || (CPY_STM32F7)
+#if CPY_TCM
 
 // Device memories must be accessed in order.
 #define DEVICE 2
@@ -140,7 +140,7 @@ __attribute__((used, naked)) void Reset_Handler(void) {
     __enable_irq();
     main();
 }
-#endif // end H7 specific code
+#endif // end TCM specific code
 
 // Low power clock variables
 static volatile uint32_t systick_ms;
@@ -287,7 +287,7 @@ uint32_t *port_heap_get_bottom(void) {
 }
 
 uint32_t *port_heap_get_top(void) {
-    #if (CPY_STM32H7) || (CPY_STM32F7)
+    #if CPY_TCM
     return &_ld_heap_end;
     #else
     return port_stack_get_limit();

diff --git a/supervisor/linker.h b/supervisor/linker.h
@@ -8,7 +8,7 @@
 
 #pragma once
 
-#if defined(IMXRT1XXX) || defined(FOMU) || defined(STM32H7) || defined(RASPBERRYPI)
+#if (defined(IMXRT1XXX) || defined(FOMU) || (defined(CPY_TCM) && CPY_TCM) || defined(RASPBERRYPI))
 #define PLACE_IN_DTCM_DATA(name) name __attribute__((section(".dtcm_data." #name)))
 #define PLACE_IN_DTCM_BSS(name) name __attribute__((section(".dtcm_bss." #name)))
 // Don't inline ITCM functions because that may pull them out of ITCM into other sections.