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Modifications for linux on rtl
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@OttG
OttG committed Jan 19, 2024
1 parent 37427a7 commit d6416ed
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17 changes: 9 additions & 8 deletions Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -143,9 +143,9 @@ else
$(warning XCELIUM_HOME not set which is necessary for compiling DPIs when using XCELIUM)
endif

#core/include/$(target)_config_pkg.sv
# this list contains the standalone components
src := core/include/$(target)_config_pkg.sv \
$(if $(spike-tandem),verif/tb/core/rvfi_pkg.sv) \
src := $(if $(spike-tandem),verif/tb/core/rvfi_pkg.sv) \
$(if $(spike-tandem),corev_apu/tb/common/spike.sv) \
corev_apu/src/ariane.sv \
$(wildcard corev_apu/bootrom/*.sv) \
Expand Down Expand Up @@ -297,7 +297,7 @@ vcs: vcs_build
-sv_lib ../work-dpi/ariane_dpi | tee vcs.log

# Build the TB and module using QuestaSim
build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ariane_dpi.so
build: $(library) $(library)/.build-srcs $(library)/.build-tb #$(dpi-library)/ariane_dpi.so
# Optimize top level
$(VOPT) $(compile_flag) -work $(library) $(top_level) -o $(top_level)_optimized +acc -check_synthesis

Expand All @@ -324,10 +324,10 @@ $(dpi-library)/%.o: corev_apu/tb/dpi/%.cc $(dpi_hdr)
mkdir -p $(dpi-library)
$(CXX) -shared -fPIC -Bsymbolic $(CFLAGS) -c $< -o $@

$(dpi-library)/ariane_dpi.so: $(dpi)
mkdir -p $(dpi-library)
# Compile C-code and generate .so file
$(CXX) -shared -m64 -o $(dpi-library)/ariane_dpi.so $? -L$(RISCV)/lib -L$(SPIKE_INSTALL_DIR)/lib -Wl,-rpath,$(RISCV)/lib -Wl,-rpath,$(SPIKE_INSTALL_DIR)/lib -lfesvr -lriscv
# $(dpi-library)/ariane_dpi.so: $(dpi)
# mkdir -p $(dpi-library)
# # Compile C-code and generate .so file
# $(CXX) -shared -m64 -o $(dpi-library)/ariane_dpi.so $? -L$(RISCV)/lib -L$(SPIKE_INSTALL_DIR)/lib -Wl,-rpath,$(RISCV)/lib -Wl,-rpath,$(SPIKE_INSTALL_DIR)/lib -lfesvr -lriscv

# single test runs on Questa can be started by calling make <testname>, e.g. make towers.riscv
# the test names are defined in ci/riscv-asm-tests.list, and in ci/riscv-benchmarks.list
Expand All @@ -337,9 +337,10 @@ generate-trace-vsim:
make sim preload=$(preload) elf_file= batch-mode=1
make generate-trace

#-sv_lib $(dpi-library)/ariane_dpi
sim: build
$(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) $(QUESTASIM_FLAGS) -gblso $(SPIKE_INSTALL_DIR)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) $(QUESTASIM_FLAGS) -gblso $(SPIKE_INSTALL_DIR)/lib/libfesvr.so \
${top_level}_optimized +permissive-off ++$(elf_file) ++$(target-options) | tee sim.log

$(riscv-asm-tests): build
Expand Down
90 changes: 90 additions & 0 deletions common/local/util/sram_pulp.sv
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Original file line number Diff line number Diff line change
@@ -0,0 +1,90 @@
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Author: Florian Zaruba <[email protected]>, ETH Zurich
// Michael Schaffner <[email protected]>, ETH Zurich
// Nils Wistoff <[email protected]>, ETH Zurich
// Date: 15.08.2018
// Description: generic tc_sram wrapper for CVA6
//
// Note: the wrapped module contains two different implementations for
// ALTERA and XILINX tools, since these follow different coding styles for
// inferrable RAMS with byte enable. define `FPGA_TARGET_XILINX or
// `FPGA_TARGET_ALTERA in your build environment (default is ALTERA)

module sram #(
parameter DATA_WIDTH = 64,
parameter BYTE_WIDTH = 8,
parameter USER_WIDTH = 1,
parameter USER_EN = 0,
parameter NUM_WORDS = 1024,
parameter SIM_INIT = "none",
parameter OUT_REGS = 0 // enables output registers in FPGA macro (read lat = 2)
)(
input logic clk_i,
input logic rst_ni,
input logic req_i,
input logic we_i,
input logic [$clog2(NUM_WORDS)-1:0] addr_i,
input logic [USER_WIDTH-1:0] wuser_i,
input logic [DATA_WIDTH-1:0] wdata_i,
input logic [(DATA_WIDTH+BYTE_WIDTH-1)/BYTE_WIDTH-1:0] be_i,
output logic [USER_WIDTH-1:0] ruser_o,
output logic [DATA_WIDTH-1:0] rdata_o
);

tc_sram #(
.NumWords ( NUM_WORDS ),
.DataWidth ( DATA_WIDTH ),
.ByteWidth ( BYTE_WIDTH ),
.NumPorts ( 32'd1 ),
.Latency ( 32'd1 ),
.SimInit ( SIM_INIT ),
.PrintSimCfg ( 1'b0 )
) i_tc_sram (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.req_i ( req_i ),
.we_i ( we_i ),
.be_i ( be_i ),
.wdata_i ( wdata_i ),
.addr_i ( addr_i ),
.rdata_o ( rdata_o )
);

if (USER_EN > 0) begin : gen_mem_user
tc_sram #(
.NumWords ( NUM_WORDS ),
.DataWidth ( DATA_WIDTH ),
.ByteWidth ( BYTE_WIDTH ),
.NumPorts ( 32'd1 ),
.Latency ( 32'd1 ),
.SimInit ( SIM_INIT ),
.PrintSimCfg ( 1'b0 )
) i_tc_sram_user (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.req_i ( req_i ),
.we_i ( we_i ),
.be_i ( be_i ),
.wdata_i ( wuser_i ),
.addr_i ( addr_i ),
.rdata_o ( ruser_o )
);

if (USER_WIDTH != DATA_WIDTH) begin : gen_err_data_user_width
$fatal(1, "sram_pulp: USER_WIDTH needs to be equal to DATA_WIDTH (if USER_EN is set).");
end

end else begin
assign ruser_o = '0;
end

endmodule : sram
3 changes: 2 additions & 1 deletion core/Flist.cva6
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Original file line number Diff line number Diff line change
Expand Up @@ -179,7 +179,8 @@ ${CVA6_REPO_DIR}/common/local/util/instr_tracer_if.sv
${CVA6_REPO_DIR}/common/local/util/instr_tracer.sv
${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv
${CVA6_REPO_DIR}/common/local/util/sram.sv
${CVA6_REPO_DIR}/common/local/util/sram_pulp.sv
//${CVA6_REPO_DIR}/common/local/util/sram.sv

// MMU Sv39
${CVA6_REPO_DIR}/core/mmu_sv39/mmu.sv
Expand Down
100 changes: 44 additions & 56 deletions corev_apu/tb/ariane_tb.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -22,9 +22,9 @@ import uvm_pkg::*;
`define MAIN_MEM(P) dut.i_sram.gen_cut[0].i_tc_sram_wrapper.i_tc_sram.init_val[(``P``)]
// `define USER_MEM(P) dut.i_sram.gen_cut[0].gen_mem.gen_mem_user.i_tc_sram_wrapper_user.i_tc_sram.init_val[(``P``)]

import "DPI-C" function read_elf(input string filename);
import "DPI-C" function byte get_section(output longint address, output longint len);
import "DPI-C" context function void read_section_sv(input longint address, inout byte buffer[]);
// import "DPI-C" function read_elf(input string filename);
// import "DPI-C" function byte get_section(output longint address, output longint len);
// import "DPI-C" context function void read_section_sv(input longint address, inout byte buffer[]);

module ariane_tb;

Expand Down Expand Up @@ -59,11 +59,11 @@ module ariane_tb;

static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst();

localparam int unsigned CLOCK_PERIOD = 20ns;
localparam int unsigned CLOCK_PERIOD = 25ns;
// toggle with RTC period
localparam int unsigned RTC_CLOCK_PERIOD = 30.517us;

localparam NUM_WORDS = 2**16;
localparam NUM_WORDS = 2**25;
logic clk_i;
logic rst_ni;
logic rtc_i;
Expand All @@ -81,7 +81,7 @@ module ariane_tb;
.rvfi_instr_t ( rvfi_instr_t ),
//
.NUM_WORDS ( NUM_WORDS ),
.InclSimDTM ( 1'b1 ),
.InclSimDTM ( 1'b0 ),
.StallRandomOutput ( 1'b0 ),
.StallRandomInput ( 1'b0 )
) dut (
Expand All @@ -93,19 +93,14 @@ module ariane_tb;

// Clock process
initial begin
clk_i = 1'b0;
rst_ni = 1'b0;
clk_i = 1'b0;
rst_ni = 1'b0;
repeat(8)
#(CLOCK_PERIOD/2) clk_i = ~clk_i;
rst_ni = 1'b1;
forever begin
#(CLOCK_PERIOD/2) clk_i = 1'b1;
#(CLOCK_PERIOD/2) clk_i = 1'b0;

//if (cycles > max_cycles)
// $fatal(1, "Simulation reached maximum cycle count of %d", max_cycles);

cycles++;
end
end

Expand All @@ -117,60 +112,53 @@ module ariane_tb;
end
end

// Detect the end of the simulation

logic [31:0] exit_val;

initial begin

int fd;

forever begin

wait (exit_o[0]);
wait (exit_val[0]);

if ((exit_o >> 1)) begin
`uvm_error( "Core Test", $sformatf("*** FAILED *** (tohost = %0d)", (exit_o >> 1)))
fd = $fopen("result.rpt", "w");

if ((exit_val >> 1)) begin
$error("*** FAILED *** (tohost = %0d)", (exit_val >> 1));
$fdisplay(fd, "FAIL");
$fdisplay(fd, "return code: 0x%x", (exit_val >> 1));
end else begin
`uvm_info( "Core Test", $sformatf("*** SUCCESS *** (tohost = %0d)", (exit_o >> 1)), UVM_LOW)
$info("*** SUCCESS *** (tohost = %0d)", (exit_val >> 1));
$fdisplay(fd, "PASS");
end

$fclose(fd);

$finish();
end
end

// for faster simulation we can directly preload the ELF
// Note that we are loosing the capabilities to use risc-fesvr though
// Memory initialisation

initial begin
automatic logic [7:0][7:0] mem_row;
longint address, load_address, last_load_address, len;
byte buffer[];
void'(uvcl.get_arg_value("+elf_file=", binary));

if (binary != "") begin
`uvm_info( "Core Test", $sformatf("Preloading ELF: %s", binary), UVM_LOW)

void'(read_elf(binary));
// wait with preloading, otherwise randomization will overwrite the existing value
wait(clk_i);

last_load_address = 'hFFFFFFFF;
// while there are more sections to process
while (get_section(address, len)) begin
automatic int num_words = (len+7)/8;
`uvm_info( "Core Test", $sformatf("Loading Address: %x, Length: %x", address, len), UVM_LOW)
buffer = new [num_words*8];
void'(read_section_sv(address, buffer));
// preload memories
// 64-bit
for (int i = 0; i < num_words; i++) begin
mem_row = '0;
for (int j = 0; j < 8; j++) begin
mem_row[j] = buffer[i*8 + j];
end
load_address = (address[23:0] >> 3) + i;
if (load_address != last_load_address) begin
`MAIN_MEM(load_address) = mem_row;
last_load_address = load_address;
end else begin
`uvm_info( "Debug info", $sformatf(" Address: %x Already Loaded! ELF file might have less than 64 bits granularity on segments.", load_address), UVM_LOW)
end

end
end
end
integer file;
integer error;
static string mem_init_file = "main.hex";
static string dtb_file = "dtb-right.mem";

@(posedge rst_ni);
#2

// Load binary to SRAM
$readmemh(mem_init_file, dut.i_sram.i_tc_sram.sram);
// Need to add the load of the DTB
$display("I loaded!\n");

$readmemh(dtb_file, dut.i_sram.i_tc_sram.sram, 'h30_0000);
// Need to set the PC to the entry point of linux
end

endmodule
44 changes: 41 additions & 3 deletions corev_apu/tb/ariane_testharness.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -470,6 +470,30 @@ module ariane_testharness #(
.data_i ( rdata )
);

// sram #(
// .DATA_WIDTH ( AXI_DATA_WIDTH ),
// .USER_WIDTH ( AXI_USER_WIDTH ),
// .USER_EN ( AXI_USER_EN ),
// `ifdef VERILATOR
// .SIM_INIT ( "none" ),
// `else
// .SIM_INIT ( "zeros" ),
// `endif
// .NUM_WORDS ( NUM_WORDS )
// ) i_sram (
// .clk_i ( clk_i ),
// .rst_ni ( rst_ni ),
// .req_i ( req ),
// .we_i ( we ),
// .addr_i ( addr[$clog2(NUM_WORDS)-1+$clog2(AXI_DATA_WIDTH/8):$clog2(AXI_DATA_WIDTH/8)] ),
// .wuser_i ( wuser ),
// .wdata_i ( wdata ),
// .be_i ( be ),
// .ruser_o ( ruser ),
// .rdata_o ( rdata )
// );


sram #(
.DATA_WIDTH ( AXI_DATA_WIDTH ),
.USER_WIDTH ( AXI_USER_WIDTH ),
Expand All @@ -478,6 +502,9 @@ module ariane_testharness #(
.SIM_INIT ( "none" ),
`else
.SIM_INIT ( "zeros" ),
`endif
`ifdef DROMAJO
.DROMAJO_RAM (1),
`endif
.NUM_WORDS ( NUM_WORDS )
) i_sram (
Expand All @@ -493,6 +520,7 @@ module ariane_testharness #(
.rdata_o ( rdata )
);


// ---------------
// AXI Xbar
// ---------------
Expand Down Expand Up @@ -551,6 +579,16 @@ module ariane_testharness #(
ariane_axi_soc::req_slv_t axi_clint_req;
ariane_axi_soc::resp_slv_t axi_clint_resp;

logic rtc;

always_ff @(posedge clk_i or negedge ndmreset_n) begin : rtc_clk
if (!ndmreset_n) begin
rtc <= 1'b0;
end else begin
rtc <= clk_i ^ 1'b1;
end
end

clint #(
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
Expand All @@ -564,7 +602,7 @@ module ariane_testharness #(
.testmode_i ( test_en ),
.axi_req_i ( axi_clint_req ),
.axi_resp_o ( axi_clint_resp ),
.rtc_i ( rtc_i ),
.rtc_i ( rtc ),
.timer_irq_o ( timer_irq ),
.ipi_o ( ipi )
);
Expand Down Expand Up @@ -618,7 +656,7 @@ module ariane_testharness #(
.spi_ss ( )
);

uart_bus #(.BAUD_RATE(115200), .PARITY_EN(0)) i_uart_bus (.rx(tx), .tx(rx), .rx_en(1'b1));
uart_bus #(.BAUD_RATE(38400), .PARITY_EN(0)) i_uart_bus (.rx(tx), .tx(rx), .rx_en(1'b1));

// ---------------
// Core
Expand All @@ -636,7 +674,7 @@ module ariane_testharness #(
) i_ariane (
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
.boot_addr_i ( ariane_soc::ROMBase ), // start fetching from ROM
.boot_addr_i ( ariane_soc::DRAMBase ), // start fetching from ROM
.hart_id_i ( {56'h0, hart_id} ),
.irq_i ( irqs ),
.ipi_i ( ipi ),
Expand Down
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