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ppa(LRQ): reduce LRQ entries #4082

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ppa(LRQ): reduce LRQ entries #4082

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2 changes: 1 addition & 1 deletion src/main/scala/xiangshan/Parameters.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -167,7 +167,7 @@ case class XSCoreParameters
LoadQueueRARSize: Int = 64,
LoadQueueRAWSize: Int = 32, // NOTE: make sure that LoadQueueRAWSize is power of 2.
RollbackGroupSize: Int = 8,
LoadQueueReplaySize: Int = 72,
LoadQueueReplaySize: Int = 48,
LoadUncacheBufferSize: Int = 4,
LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks
StoreQueueSize: Int = 56,
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8 changes: 2 additions & 6 deletions src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
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Expand Up @@ -278,15 +278,15 @@ class LoadQueueReplay(implicit p: Parameters) extends XSModule
val hasExceptions = io.enq.map(enq => ExceptionNO.selectByFu(enq.bits.uop.exceptionVec, LduCfg).asUInt.orR && !enq.bits.tlbMiss)
val loadReplay = io.enq.map(enq => enq.bits.isLoadReplay)
val needEnqueue = VecInit((0 until LoadPipelineWidth).map(w => {
canEnqueue(w) && !cancelEnq(w) && needReplay(w) && !hasExceptions(w)
canEnqueue(w) && !cancelEnq(w) && needReplay(w) && !hasExceptions(w) && !io.lqFull
}))
val newEnqueue = Wire(Vec(LoadPipelineWidth, Bool()))
val canFreeVec = VecInit((0 until LoadPipelineWidth).map(w => {
canEnqueue(w) && loadReplay(w) && (!needReplay(w) || hasExceptions(w))
}))

// select LoadPipelineWidth valid index.
val lqFull = freeList.io.empty
val lqFull = (LoadQueueReplaySize.U - freeList.io.validCount) < 6.U
val lqFreeNums = freeList.io.validCount

// replay logic
Expand Down Expand Up @@ -603,10 +603,6 @@ class LoadQueueReplay(implicit p: Parameters) extends XSModule
// init
freeMaskVec.map(e => e := false.B)

// LoadQueueReplay can't backpressure.
// We think LoadQueueReplay can always enter, as long as it is the same size as VirtualLoadQueue.
assert(freeList.io.canAllocate.reduce(_ || _) || !io.enq.map(_.valid).reduce(_ || _), s"LoadQueueReplay Overflow")

// Allocate logic
needEnqueue.zip(newEnqueue).zip(io.enq).map {
case ((needEnq, newEnq), enq) =>
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3 changes: 2 additions & 1 deletion src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
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Expand Up @@ -1525,7 +1525,8 @@ class LoadUnit(implicit p: Parameters) extends XSModule
io.fast_rep_out.bits.delayedLoadError := s3_hw_err

val s3_vp_match_fail = GatedValidRegNext(s2_fwd_vp_match_invalid) && s3_troublem
val s3_rep_frm_fetch = s3_vp_match_fail
val s3_rep_frm_fetch_rep_full = io.lq_rep_full && s3_in.rep_info.need_rep && !s3_in.isLoadReplay
val s3_rep_frm_fetch = s3_vp_match_fail || s3_rep_frm_fetch_rep_full
val s3_ldld_rep_inst =
io.lsq.ldld_nuke_query.resp.valid &&
io.lsq.ldld_nuke_query.resp.bits.rep_frm_fetch &&
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