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Feat(smcntrpmf): support smcntrpmf extension #4019

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Feat(smcntrpmf): support smcntrpmf extension #4019

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2208f17
feat(Smcntrpmf): support Smcntrpmf extension
wissygh Dec 10, 2024
a1a2dfc
submodule(rocket-chip): bump rocket-chip to support Smcntrpmf extension
wissygh Dec 10, 2024
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2 changes: 1 addition & 1 deletion rocket-chip
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Submodule rocket-chip updated 1 files
+2 −0 src/main/scala/rocket/Instructions.scala
33 changes: 22 additions & 11 deletions src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -297,21 +297,21 @@ trait MachineLevel { self: NewCSR =>
val MML = RO( 0) // Smepmp
})).setAddr(CSRs.mseccfg)

val mcycle = Module(new CSRModule("Mcycle") with HasMachineCounterControlBundle {
val mcycle = Module(new CSRModule("Mcycle") with HasMachineCounterControlBundle with SmcntrpmfBundle {
when(w.wen) {
reg := w.wdata
}.elsewhen(!this.mcountinhibit.CY.asUInt.asBool) {
}.elsewhen(!this.mcountinhibit.CY.asUInt.asBool && countingEn) {
reg := reg.ALL.asUInt + 1.U
}.otherwise {
reg := reg
}
}).setAddr(CSRs.mcycle)


val minstret = Module(new CSRModule("Minstret") with HasMachineCounterControlBundle with HasRobCommitBundle {
val minstret = Module(new CSRModule("Minstret") with HasMachineCounterControlBundle with HasRobCommitBundle with SmcntrpmfBundle {
when(w.wen) {
reg := w.wdata
}.elsewhen(!this.mcountinhibit.IR && robCommit.instNum.valid) {
}.elsewhen(!this.mcountinhibit.IR && robCommit.instNum.valid && countingEn) {
reg := reg.ALL.asUInt + robCommit.instNum.bits
}.otherwise {
reg := reg
Expand All @@ -335,6 +335,12 @@ trait MachineLevel { self: NewCSR =>
}).setAddr(CSRs.mhpmcounter3 - 3 + num)
)

val mcyclecfg = Module(new CSRModule("Mcyclecfg", new EventInhibitBundle))
.setAddr(CSRs.mcyclecfg)

val minstretcfg = Module(new CSRModule("Minstretcfg", new EventInhibitBundle))
.setAddr(CSRs.minstretcfg)

val mvendorid = Module(new CSRModule("Mvendorid") { rdata := 0.U })
.setAddr(CSRs.mvendorid)

Expand Down Expand Up @@ -417,6 +423,8 @@ trait MachineLevel { self: NewCSR =>
mncause,
mnstatus,
mnscratch,
mcyclecfg,
minstretcfg,
) ++ mhpmevents ++ mhpmcounters

val machineLevelCSRMap: SeqMap[Int, (CSRAddrWriteBundle[_], UInt)] = SeqMap.from(
Expand Down Expand Up @@ -674,13 +682,16 @@ class MipToMvip extends IpValidBundle {
this.SEIP.bits.setRW()
}

class MhpmeventBundle extends CSRBundle {
val OF = RW(63).withReset(0.U)
class EventInhibitBundle extends CSRBundle {
val MINH = RW(62).withReset(0.U)
val SINH = RW(61).withReset(0.U)
val UINH = RW(60).withReset(0.U)
val VSINH = RW(59).withReset(0.U)
val VUINH = RW(58).withReset(0.U)
}

class MhpmeventBundle extends EventInhibitBundle {
val OF = RW(63).withReset(0.U)
val OPTYPE2 = OPTYPE(54, 50, wNoFilter).withReset(OPTYPE.OR)
val OPTYPE1 = OPTYPE(49, 45, wNoFilter).withReset(OPTYPE.OR)
val OPTYPE0 = OPTYPE(44, 40, wNoFilter).withReset(OPTYPE.OR)
Expand Down Expand Up @@ -753,10 +764,10 @@ trait HasPerfCounterBundle { self: CSRModule[_] =>
val toMhpmeventOF = IO(Output(Bool()))
}

trait HasPerfEventBundle { self: CSRModule[_] =>
val perfEvents = IO(Input(Vec(perfCntNum, UInt(XLEN.W))))
}

trait HasLocalInterruptReqBundle { self: CSRModule[_] =>
val lcofiReq = IO(Input(Bool()))
}
}

trait SmcntrpmfBundle { self: CSRModule[_] =>
val countingEn = IO(Input(Bool()))
}
20 changes: 20 additions & 0 deletions src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -1175,6 +1175,26 @@ class NewCSR(implicit val p: Parameters) extends Module
m.lcofiReq := lcofiReq
case _ =>
}
// Smcntrpmf extension
mcycle match {
case m: SmcntrpmfBundle =>
m.countingEn := (privState.isModeM && !mcyclecfg.regOut.MINH) ||
(privState.isModeHS && !mcyclecfg.regOut.SINH) ||
(privState.isModeHU && !mcyclecfg.regOut.UINH) ||
(privState.isModeVS && !mcyclecfg.regOut.VSINH) ||
(privState.isModeVU && !mcyclecfg.regOut.VUINH)
case _ =>
}

minstret match {
case m: SmcntrpmfBundle =>
m.countingEn := (privState.isModeM && !minstretcfg.regOut.MINH) ||
(privState.isModeHS && !minstretcfg.regOut.SINH) ||
(privState.isModeHU && !minstretcfg.regOut.UINH) ||
(privState.isModeVS && !minstretcfg.regOut.VSINH) ||
(privState.isModeVU && !minstretcfg.regOut.VUINH)
case _ =>
}
/**
* perf_end
*/
Expand Down
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