tmp

OpenXiangShan · Dec 27, 2024 · d8331d2 · d8331d2
1 parent 2658098
commit d8331d2
Showing 1 changed file with 12 additions and 9 deletions.
diff --git a/src/main/scala/xiangshan/mem/vector/VSplit.scala b/src/main/scala/xiangshan/mem/vector/VSplit.scala
@@ -218,13 +218,16 @@ class VSplitPipeline(isVStore: Boolean = false)(implicit p: Parameters) extends
     s1_nfields << s1_eew // for unit-stride load, stride = eew * NFIELDS
   )
 
-  val stride     = Mux(isIndexed(s1_instType), s1_stride, s1_notIndexedStride).asUInt // if is index instructions, get index when split
-  val uopOffset  = genVUopOffset(s1_instType, s1_fof, s1_uopidx, s1_nf, s1_eew, stride, s1_alignedType)
-  val activeNum  = Mux(s1_in.preIsSplit, PopCount(s1_in.flowMask), s1_flowNum)
+  val stride            = Mux(isIndexed(s1_instType), s1_stride, s1_notIndexedStride).asUInt // if is index instructions, get index when split
+  val uopOffset         = genVUopOffset(s1_instType, s1_fof, s1_uopidx, s1_nf, s1_eew, stride, s1_alignedType)
   // for Unit-Stride, if uop's addr is aligned with 128-bits, split it to one flow, otherwise split two
-  val usLowBitsAddr    = getCheckAddrLowBits(s1_in.baseAddr, maxMemByteNum) + getCheckAddrLowBits(uopOffset, maxMemByteNum)
-  val usAligned128     = (getCheckAddrLowBits(usLowBitsAddr, maxMemByteNum) === 0.U)// addr 128-bit aligned
-  val usMask           = Cat(0.U(VLENB.W), s1_in.byteMask) << getCheckAddrLowBits(usLowBitsAddr, maxMemByteNum)
+  val usLowBitsAddr     = getCheckAddrLowBits(s1_in.baseAddr, maxMemByteNum) + getCheckAddrLowBits(uopOffset, maxMemByteNum)
+  val usMask            = Cat(0.U(VLENB.W), s1_in.byteMask) << getCheckAddrLowBits(usLowBitsAddr, maxMemByteNum)
+  val usAligned128      = getCheckAddrLowBits(usLowBitsAddr, maxMemByteNum) === 0.U // addr 128-bit aligned
+  val usMaskInSingleUop = genUSSplitMask(usMask.asTypeOf(UInt(32.W)), 1.U) === 0.U
+  val usActiveNum       = Mux(usAligned128 || usMaskInSingleUop, (VecMemUnitStrideMaxFlowNum - 1).U, VecMemUnitStrideMaxFlowNum.U)
+  val activeNum         = Mux(s1_in.preIsSplit, PopCount(s1_in.flowMask), usActiveNum)
+
 
   s1_kill               := s1_in.uop.robIdx.needFlush(io.redirect)
 
@@ -400,8 +403,8 @@ abstract class VSplitBuffer(isVStore: Boolean = false)(implicit p: Parameters) e
   splitFinish := splitIdx >= (issueFlowNum - issueCount)
 
   // handshake
-  activeIssue := issueValid && allowIssue && (vecActive || !issuePreIsSplit) // active issue, current use in no unit-stride
-  inActiveIssue := issueValid && !vecActive && issuePreIsSplit
+  activeIssue := issueValid && allowIssue && vecActive // active issue, current use in no unit-stride
+  inActiveIssue := issueValid && !vecActive
   when (!issueEntry.uop.robIdx.needFlush(io.redirect)) {
     when (!splitFinish) {
       when (activeIssue || inActiveIssue) {
@@ -430,7 +433,7 @@ abstract class VSplitBuffer(isVStore: Boolean = false)(implicit p: Parameters) e
   }
 
   // out connect
-  io.out.valid := issueValid && (vecActive || !issuePreIsSplit) && (addrAligned || misalignedCanGo) // TODO: inactive unit-stride uop do not send to pipeline
+  io.out.valid := issueValid && vecActive && (addrAligned || misalignedCanGo) // TODO: inactive unit-stride uop do not send to pipeline
 
   XSPerfAccumulate("out_valid",             io.out.valid)
   XSPerfAccumulate("out_fire",              io.out.fire)