fix(csr, exception): divide the excep raised from csrrw into 2 stages

[NewPaulWalker]

Before this, we assumed that all possible exceptions during CSR read and write operations should be handled according to their priority.

Therefore, we used has_vi to record whether a virtual instruction exception exists and ensured that all illegal instruction exceptions take precedence over virtual instruction exceptions.

However, with the implementation of certain extensions like Smcsrind and Smstateen, we encounter scenarios where virtual instruction exceptions must take precedence over illegal instruction exceptions triggered.

For instance, when mstateen0.csrind is set to 1 and hstateen0.csrind is 0, a virtual instruction exception should be raised if VS mode attempts to access sireg. However, if the vsiselect value is reserved in this situation, an illegal instruction exception will be raised instead. If these checks are treated as being at the same priority level, an illegal instruction exception would ultimately be raised.

In reality, a virtual instruction exception should take precedence because when the extension is disabled, we should not even evaluate the value of vsiselect.

We should first check whether the CSR exists, is read-only, has proper permissions, and is enabled/disabled before proceeding to check indirect CSR accesses.