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ofs-2024.1-1/hw/ftile_devkit/user_guides/ug_qs_ofs_ftile/ug_qs_ofs_ftile/index.html

@@ -2660,7 +2660,7 @@
 <h1 id="getting-started-guide-open-fpga-stack-for-intel-agilex-7-fpgas-targeting-the-agilex-7-fpga-f-series-development-kit-2x-f-tile">Getting Started Guide: Open FPGA Stack for Intel Agilex 7 FPGAs Targeting the Agilex® 7 FPGA F-Series Development Kit (2x F-Tile)<a class="headerlink" href="#getting-started-guide-open-fpga-stack-for-intel-agilex-7-fpgas-targeting-the-agilex-7-fpga-f-series-development-kit-2x-f-tile" title="Permanent link">&para;</a></h1>
 <p>Last updated: <strong>May 13, 2024</strong> </p>
 <h2 id="10-about-this-document">1.0 About This Document<a class="headerlink" href="#10-about-this-document" title="Permanent link">&para;</a></h2>
-<p>The purpose of this document is to help users get started in evaluating the 2024.1-1 version of the PCIe Attach release targeting the F-Series Development Kit. This document will <strong>not</strong> cover <a href="https://ofs.github.io/ofs-2024.1-1/hw/common/board_installation/devkit_board_installation/devkit_board_installation_guidelines/">Board Installation Guidelines</a> or <a href="/ofs-2024.1-1/hw/common/sw_installation/pcie_attach/sw_install_pcie_attach.md"><abbr title="Open FPGA Stack, A modular collection of hardware platform components, open source software, and broad ecosystem support that provides a standard and scalable model for AFU and software developers to optimize and reuse their designs.">OFS</abbr> Software Installation</a>. Instead it will recommend you use a software installer to allow for fast evaluation. After reviewing this document, a user shall be able to:</p>
+<p>The purpose of this document is to help users get started in evaluating the 2024.1-1 version of the PCIe Attach release targeting the F-Series Development Kit. This document will <strong>not</strong> cover <a href="https://ofs.github.io/ofs-2024.1-1/hw/common/board_installation/devkit_board_installation/devkit_board_installation_guidelines/">Board Installation Guidelines</a> or <a href="/ofs-2024.1-1/hw/common/sw_installation/pcie_attach/sw_install_pcie_attach"><abbr title="Open FPGA Stack, A modular collection of hardware platform components, open source software, and broad ecosystem support that provides a standard and scalable model for AFU and software developers to optimize and reuse their designs.">OFS</abbr> Software Installation</a>. Instead it will recommend you use a software installer to allow for fast evaluation. After reviewing this document, a user shall be able to:</p>
 <ul>
 <li>Set up a server environment according to the Best Known Configuration (<abbr title="Best Known Configuration, The exact hardware configuration Intel has optimized and validated the solution against.">BKC</abbr>)</li>
 <li>Load and verify firmware targeting the <abbr title="FPGA Interface Manager, Provides platform management, functionality, clocks, resets and standard interfaces to host and AFUs. The FIM resides in the static region of the FPGA and contains the FPGA Management Engine (FME) and I/O ring.">FIM</abbr> and <abbr title="Accelerator Functional Unit, Hardware Accelerator implemented in FPGA logic which offloads a computational operation for an application from the CPU to improve performance. Note: An AFU region is the part of the design where an AFU may reside. This AFU may or may not be a partial reconfiguration region">AFU</abbr> regions of the AGFB027R24C2E2VR2 FPGA</li>
@@ -2958,7 +2958,7 @@ <h4 id="212-afu">2.1.2 <abbr title="Accelerator Functional Unit, Hardware Accele
 <p>The <abbr title="Accelerator Functional Unit, Hardware Accelerator implemented in FPGA logic which offloads a computational operation for an application from the CPU to improve performance. Note: An AFU region is the part of the design where an AFU may reside. This AFU may or may not be a partial reconfiguration region">AFU</abbr> has the option to consume native packets from the host or interface channels or to instantiate a shim provided by the Platform Interface Manager (<abbr title="Platform Interface Manager, An interface manager that comprises two components: a configurable platform specific interface for board developers and a collection of shims that AFU developers can use to handle clock crossing, response sorting, buffering and different protocols.">PIM</abbr>) to translate between protocols.</p>
 <p><em>Note: For more information on the Platform Interface Manager and <abbr title="Accelerator Functional Unit, Hardware Accelerator implemented in FPGA logic which offloads a computational operation for an application from the CPU to improve performance. Note: An AFU region is the part of the design where an AFU may reside. This AFU may or may not be a partial reconfiguration region">AFU</abbr> development and testing, refer to the <a href="https://ofs.github.io/ofs-2024.1-1/hw/common/user_guides/afu_dev/ug_dev_afu_ofs_agx7_pcie_attach/ug_dev_afu_ofs_agx7_pcie_attach/">Workload Developer Guide: <abbr title="Open FPGA Stack, A modular collection of hardware platform components, open source software, and broad ecosystem support that provides a standard and scalable model for AFU and software developers to optimize and reuse their designs.">OFS</abbr> for Agilex® 7 PCIe Attach FPGAs</a>.</em></p>
 <h2 id="30-board-installation-and-server-requirements">3.0 Board Installation and Server Requirements<a class="headerlink" href="#30-board-installation-and-server-requirements" title="Permanent link">&para;</a></h2>
-<p>Instructions detailing the board installation guidelines for an F-Tile Dev Kit including server BIOS settings and regulatory information can be found in the <a href="/ofs-2024.1-1/hw/common/board_installation/devkit_board_installation/devkit_board_installation_guidelines.md">Board Installation Guidelines: Intel Agilex® 7 FPGA F-Series Development Kit (2x F-Tile) and Intel Agilex® 7 FPGA I-Series Development Kit (2x R-Tile and 1xF-Tile)</a>. This document also covers the installation of a <abbr title="Joint Test Action Group, Refers to the IEEE 1149.1 JTAG standard; Another FPGA configuration methodology.">JTAG</abbr> cable, which is required for shell programming.</p>
+<p>Instructions detailing the board installation guidelines for an F-Tile Dev Kit including server BIOS settings and regulatory information can be found in the <a href="/ofs-2024.1-1/hw/common/board_installation/devkit_board_installation/devkit_board_installation_guidelines/">Board Installation Guidelines: Intel Agilex® 7 FPGA F-Series Development Kit (2x F-Tile) and Intel Agilex® 7 FPGA I-Series Development Kit (2x R-Tile and 1xF-Tile)</a>. This document also covers the installation of a <abbr title="Joint Test Action Group, Refers to the IEEE 1149.1 JTAG standard; Another FPGA configuration methodology.">JTAG</abbr> cable, which is required for shell programming.</p>
 <h2 id="40-f-series-development-kit-jtag-driver-setup">4.0 F-Series Development Kit <abbr title="Joint Test Action Group, Refers to the IEEE 1149.1 JTAG standard; Another FPGA configuration methodology.">JTAG</abbr> Driver Setup<a class="headerlink" href="#40-f-series-development-kit-jtag-driver-setup" title="Permanent link">&para;</a></h2>
 <p>A specific <abbr title="Joint Test Action Group, Refers to the IEEE 1149.1 JTAG standard; Another FPGA configuration methodology.">JTAG</abbr> driver needs to be installed on the host OS. Follow the instructions under the driver setup for Red Hat 5+ on <a href="https://www.intel.com/content/www/us/en/support/programmable/support-resources/download/dri-usb-b-lnx.html">Intel® FPGA Download Cable (formerly USB-Blaster) Driver for Linux*</a>.</p>
 <p>View the <abbr title="Joint Test Action Group, Refers to the IEEE 1149.1 JTAG standard; Another FPGA configuration methodology.">JTAG</abbr> Chain after installing the proper driver and Quartus Programmer.</p>
@@ -3004,7 +3004,7 @@ <h4 id="table-4-fim-version">Table 4: <abbr title="FPGA Interface Manager, Provi
 </tr>
 </tbody>
 </table>
-<p>You will need to download and unpack the artifact images for this release before upgrading your device. You also need to set up the F-Series Development Kit as outlined in the <a href="/ofs-2024.1-1/hw/common/board_installation/devkit_board_installation/devkit_board_installation_guidelines.md">Board Installation Guidelines: Intel Agilex® 7 FPGA F-Series Development Kit (2x F-Tile) and Intel Agilex® 7 FPGA I-Series Development Kit (2x R-Tile and 1xF-Tile)</a>. The file <code>ofs_top_hps.sof</code> is the base <abbr title="Open FPGA Stack, A modular collection of hardware platform components, open source software, and broad ecosystem support that provides a standard and scalable model for AFU and software developers to optimize and reuse their designs.">OFS</abbr> <abbr title="FPGA Interface Manager, Provides platform management, functionality, clocks, resets and standard interfaces to host and AFUs. The FIM resides in the static region of the FPGA and contains the FPGA Management Engine (FME) and I/O ring.">FIM</abbr> file. This file is loaded into the FPGA using the development kit built in USB Blaster. Please be aware this FPGA is not loaded into non-volatile storage. If the server is power cycled you will need to reload the FPGA .sof file.</p>
+<p>You will need to download and unpack the artifact images for this release before upgrading your device. You also need to set up the F-Series Development Kit as outlined in the <a href="/ofs-2024.1-1/hw/common/board_installation/devkit_board_installation/devkit_board_installation_guidelines/">Board Installation Guidelines: Intel Agilex® 7 FPGA F-Series Development Kit (2x F-Tile) and Intel Agilex® 7 FPGA I-Series Development Kit (2x R-Tile and 1xF-Tile)</a>. The file <code>ofs_top_hps.sof</code> is the base <abbr title="Open FPGA Stack, A modular collection of hardware platform components, open source software, and broad ecosystem support that provides a standard and scalable model for AFU and software developers to optimize and reuse their designs.">OFS</abbr> <abbr title="FPGA Interface Manager, Provides platform management, functionality, clocks, resets and standard interfaces to host and AFUs. The FIM resides in the static region of the FPGA and contains the FPGA Management Engine (FME) and I/O ring.">FIM</abbr> file. This file is loaded into the FPGA using the development kit built in USB Blaster. Please be aware this FPGA is not loaded into non-volatile storage. If the server is power cycled you will need to reload the FPGA .sof file.</p>
 <div class="highlight"><pre><span></span><code><a id="__codelineno-1-1" name="__codelineno-1-1" href="#__codelineno-1-1"></a>wget<span class="w"> </span>https://github.com/OFS/ofs-agx7-pcie-attach/releases/download/ofs-2024.1-1/fseries-images_ofs-2024-1-1.tar.gz
 <a id="__codelineno-1-2" name="__codelineno-1-2" href="#__codelineno-1-2"></a>tar<span class="w"> </span>xf<span class="w"> </span>fseries-dk-images.tar.gz
 <a id="__codelineno-1-3" name="__codelineno-1-3" href="#__codelineno-1-3"></a><span class="nb">cd</span><span class="w"> </span>fseries-dk-images/