ofs-2024.1-1 Release for Agilex 7 PCIe Attach Reference Shells
OFS 2024.1-1
Summary: OFS 2024.1-1 Release for Agilex® 7 PCIe Attach FPGAs
For the overall release and associated repos please review the Discussions post.
For complete documentation go to the OFS Documentation site
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Boards Targeted:
- Agilex® 7 FPGA I-Series Development Kit (2x R-Tile, F-Tile)
- Agilex® 7 FPGA F-Series Development Kit (2x F-Tile)
- Intel® FPGA SmartNIC N6001-PL/N6000-PL (P-Tile, E-Tile)
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Board Management Controller (BMC):
- MAX® 10 Nios® Firmware Version: 3.15.0 (Intel® FPGA SmartNIC N6001-PL/N6000-PL only)
- MAX® 10 Build Version: 3.15.0 (Intel® FPGA SmartNIC N6001-PL/N6000-PL only)
Agilex® 7 FPGA F-Series and I-Series Development Kits do not utilize an OFS compatible BMC, thus certain features such as remote system update are not supported.
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Quartus® Prime Pro Version: 23.4
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Quartus Prime Pro License File: quartus-0.0-0.02iofs-linux.run
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Quartus Prime Pro Patch: Patch 0.17 (PCIe). Note that patches are found at the bottom of this page in the assets.
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OS Tested: Red Hat® Enterprise Linux® 8.6
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OPAE Version: 2.12.0-4
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Kernel Version: 6.1.78-lts
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OFS Agilex® 7 PCIe Attach FIM Github Branch: https://github.com/OFS/ofs-agx7-pcie-attach/tree/release/ofs-2024.1
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OFS Agilex® 7 PCIe Attach FIM Github Tag: https://github.com/OFS/ofs-agx7-pcie-attach/releases/tag/ofs-2024.1-1
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OFS FIM_COMMON Github Tag: https://github.com/OFS/ofs-fim-common/releases/tag/ofs-2024.1-1
OPAE SDK:
- OPAE SDK Branch: https://github.com/OFS/opae-sdk/tree/release/2.12.0
- OPAE SDK Tag: https://github.com/OFS/opae-sdk/releases/tag/2.12.0-5
OPAE SIM:
- OPAE SIM Branch: https://github.com/OFS/opae-sim/tree/release/2.12.0
- OPAE SIM Tag: https://github.com/OFS/opae-sim/releases/tag/2.12.0-1
Driver:
- Kernel Driver Branch: https://github.com/OFS/linux-dfl/tree/fpga-ofs-dev-6.1-lts
- Kernel Driver Tag: https://github.com/OFS/linux-dfl/releases/tag/ofs-2024.1-6.1-2
This page provides up-to-date information about the Open FPGA Stack (OFS) for Agilex® 7 PCIe Attach devices. This project targets the:
- Agilex® 7 FPGA I-Series Development Kit (2xR-Tile, F-Tile)
- Agilex® 7 FPGA F-Series Development Kit (2xF-Tile)
- Intel® FPGA SmartNIC N6001-PL/N6000-PL
The summary of OFS framework features are shown below. To find out more about these platforms refer to the documentation below:
- Intel® FPGA SmartNIC N6001-PL Platform Product Brief
- Intel® FPGA SmartNIC N6000-PL
- Agilex 7 FPGA F-Series Development Kit (2xF-Tile) User Guide
- Agilex 7 FPGA I-Series Development Kit (2xR-Tile, F-Tile) User Guide
OFS Agilex®7 PCIe Attach FIM Key Features
| Key Feature | I-Series (2xR-Tile, 1xF-Tile) | F-Series (2xF-Tile) | F-Series (1xP-Tile, 1xE-Tile) |
|---|---|---|---|
| Target OPN | AGIB027R29A1E2VR3 | AGFB027R24C2E2VR2 | AGFB014R24A2E2V |
| PCIe | R-tile PCIe* Gen5x8 | F-tile PCIe* Gen4x16 | P-tile PCIe* Gen4x16 |
| Virtualization | 5 physical functions/3 virtual functions with ability to expand | 5 physical functions/3 virtual functions with ability to expand | 5 physical functions/3 virtual functions with ability to expand |
| Memory | 4 Fabric DDR4 channels, x64 (no ECC), 2666 MHz, 8GB | 3 DDR Channels: • One HPS DDR4 bank, x40 (x32 Data and x8 ECC), 2400 MHz, 1GB each • Two Fabric DDR4 banks, x64 (no ECC), 2400 MHz, 8GB |
5 DDR Channels: • One HPS DDR4 bank, x40 (x32 Data and x8 ECC), 1200 MHz, 1GB each • Four Fabric DDR4 banks, x32 (no ECC), 1200 MHz, 4GB |
| Ethernet | 2x4x25GbE, 2x200GbE, 2x400GbE | 2x4x25GbE | • N6001-PL: 2x4x25GbE, 2x4x10GbE, or 2x100GbE • N6000-PL: 4x100GbE |
| Hard Processor System | Not enabled | 64-bit quad core Arm® Cortex®-A53 MPCore with integrated peripherals. | 64-bit quad core Arm® Cortex®-A53 MPCore with integrated peripherals. |
| Configuration and Board Manageability | • FPGA Management Engine that provides general control of common FPGA tasks (ex. error reporting, partial reconfiguration) • Platform Management Controller Interface (PMCI) Module for Board Management Controller |
• FPGA Management Engine that provides general control of common FPGA tasks (ex. error reporting, partial reconfiguration) • Platform Controller Management Interface (PMCI) Module for Board Management Controller |
• FPGA Management Engine that provides general control of common FPGA tasks (ex. error reporting, partial reconfiguration) • Platform Controller Management Interface (PMCI) Module for Board Management Controller |
| Partial Reconfiguration | Supported | Supported | Supported |
| OneAPI | OneAPI Acceleration Support Package (ASP) provided with compiled FIM to support OneAPI Runtime | OneAPI Acceleration Support Package (ASP) provided with compiled FIM to support OneAPI Runtime | OneAPI Acceleration Support Package (ASP) provided with compiled FIM to support OneAPI Runtime |
| Software Support | • Linux DFL drivers targeting OFS FIMs • OPAE Software Development Kit • OPAE Tools |
• Linux DFL drivers targeting OFS FIMs • OPAE Software Development Kit • OPAE Tools |
• Linux DFL drivers targeting OFS FIMs • OPAE Software Development Kit • OPAE Tools |
| Target Board | Agilex® 7 FPGA I-Series Development Kit (2xR-Tile, F-Tile) | Agilex® 7 FPGA F-Series Development Kit (2x F-Tile) | • Intel® FPGA SmartNIC N6001-PL • Intel® 7 FPGA SmartNIC N6000-PL |
The OFS hardware framework also provides:
- Support for unit test simulation (using Synopsys® VCS® or Siemens® Questa™ simulators)
- UVM support using Synopsys® VCS®
- Host exercisers that allow you to test interfaces on the FPGA
The OFS software framework provides:
- FPGA platform Linux drivers that are being upstreamed to linux.org
- A programmable software development kit and userspace tools for managing the FPGA
Important: If you would like to begin evaluating the default shell that can be built from this repository, please scroll down to the "assets" accordion button below which contains the FPGA binary/POF/SOF along with the applicable Linux driver and Open Programmable Acceleration Engine (OPAE) software development kit (SDK) packages.
New Updates for ofs-2024.1-1 Release
- Quartus Version moved to 23.4
- I-Series Development Kit Reference FIM Memory interface expanded from 2 to 4 channels.
- Added 2 PF (physical function) shell support for Agilex 7 PCIe Attach F-Series and I-Series Development Kits that provides capability for passing a PF into a VM and additionally Partial reconfiguration functionality on a PF.
- Added support for Intel FPGA SmartNIC N6000-PL
Known Issues
This table describes the known issues for the 2024.1 OFS Release targeting Agilex® 7 devices.
| ID | Known Issues | Workaround | Status | Platform Target Affected |
|---|---|---|---|---|
| - | R-tile Agilex PCIe Attach Reference FIM does not support UVM simulation. Only unit test simulation is available. | None | Fixed in a future release of OFS | I-Series Development Kit |
| - | The R-Tile PCIe attach design requires a [16550 UART IP license file](https://github.com/OFS/ofs-agx7-pcie-attach/tree/release/ofs-2024.1/license) to be installed in Quartus Prime Pro even though it is not used in the design. | None | Fixed in a future release of OFS | I-Series Development Kit |
| 14021023150 | The fpgainfo phy command reports QSFP as not connected even if Ethernet ports are up because QSFP status is not routed to the FPGA in the Agilex® 7 I-Series Development Kit. | Refer to the Port Status listed in the command to observe the link status. | No future fix. | I-Series Development Kit |
| 14020129685 | The hssi_loopback command is currently not supported when FIM Ethernet configuration is 2x100GbE. | None | Fixed in a future release of OFS. | Intel® FPGA SmartNIC N6001-PL |
| 14018364039 | The OPAE command fpgainfo bmc and fpgainfo temp display a "CVL" field that is not utilized by the design. | None. Ignore "CVL" listings. | Fixed in a future release of OFS. | Intel® FPGA SmartNIC N6001-PL |
| 14021569447 | Build script fails if the HSSI OFSS file is not provided when building F-series or I-series dev kit designs. | Specify HSSI OFSS file when building, either in top level OFSS file or in the command when running the build script. | Fixed in a future release of OFS. | I-Series and F-Series Development Kits |
| 14021771678 | Intel® FPGA SmartNIC N6000-PL FIM has incorrect subsystem ID. | Change the subsystem ID value in the PCIe Sub-System IP from `1771` to `1770`. | Fixed in a future release of OFS. | Intel® FPGA SmartNIC N6000-PL |
| 14021789829 | Reset synchronizers fail recovery/removal timing when building N6000 and N6001 designs with more than 8 Ethernet channels. | Add the following constraints to $OFS_ROOTDIR/syn/shared_config/top.sdc: add_reset_sync_sdc {afu_top|*|*|*|*|*he_hssi_inst|GenCPR[*].hssi_data_sync|fifo|dcfifo|dcfifo_component|auto_generated|rdaclr|*|clrn} add_reset_sync_sdc {afu_top|*|*|*|*|*he_hssi_inst|GenCPR[*].hssi_data_sync|fifo|rst_rclk_resync|resync_chains[*].*|*|clrn} | Fixed in a future release of OFS. | Intel® FPGA SmartNIC N6001-PL/N6000-PL |
Resolved Issues
| ID | Resolved Issue | Platform Target Affected |
|---|---|---|
| 14020467906 | Compiling an F-Tile PCIe Attach design with a 100GbE configuration results in a build failure | F-Series Development Kit |
| 14020113416 | Simulations of Ethernet Subsystem in 10GbE configuration show rx_tvalid in an unknown state upon reset. 10GbE simulation is currently not supported | Intel® FPGA SmartNIC N6001-PL |
Important Notes
The following section provides important information about this release:
| ID | Important Notes |
|---|---|
| - | For the F-Series Development Kit (2xF-tile) shell design, the reference clock for the Ethernet subsystem uses reference Clock 6 (QSFPDD REFCLK), which is only accessible from FGT Quads 2 and 3. If you wish to use FGT Quads 0 or 1, you will need to change the reference clock to one that is accessible by all FGT Quads (e.g. Reference Clock 2 (QSFP Global REFCLK)). |
| - | When using the PF/VF configuration tool to reconfigure the PF/VF MUX, you must keep at least: • One (1) physical function and one (1) virtual function on PF0. OR • Two (2) physical functions. All other PFs and VFs can be removed if desired. |
| 15012246661 | When enabling cable hotplug IP and ANLT, the E-tile recipe resulting from the ANLT initialization flow is over-written by the hotplug initialization flow. If you require a custom ANLT recipe, then you cannot use hotplug at this time. You can disable hotplug by writing 1 to index-0 of HSSI Hotplug Debug Control Register (offset 0x600B4) followed by a port level reset or analog reset. |
| 15012406417 | If using the Intel® FPGA SmartNIC N6001-PL Platform (SKU2) for evaluation of the OFS release, ensure DIP Switch SW1.4 on the board is set to convey the correct board type or the OPAE commands could display invalid temperature values for an Intel® NIC E810 (SKU1) which is not populated on the SKU2 board. For Intel® FPGA SmartNIC N6001-PL Platform (SKU2), SW1.4 must be off (pointing towards the PCIe goldfinger). Note that a BMC reset is required if you must flip the switch to the correct setting. |
| 14020225084 | The regress_run.py simulation script runs a superset of simulation tests for all configurations available in the ofs-agx7-pcie-attach repository. You can customize the regress_run.py script to run only the tests applicable to your design by using the -k list option in the script which directs the regression to only pick up tests you have listed in your list.txt file. Please refer to the FPGA Interface Manager Development Guide for more details. |