Add embedded SoC FPGA support #115
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Some comments: Before the merge, It requires a patch of UUID splitting (uuid.h and uuidlib.h) where common definitions moved and added __uuid_is_valid(*guid_string) the new wrapper function |
Added the helper functions to parse the passed character string to GUID/UUID and compare with passed GUID. Signed-off-by: Basheer Ahmed Muddebihal <[email protected]>
In the modalias table, dfl devices use the type id and feature id to
create the dfl device string entry "dfl:t0000f0009*". This patch adds
support for the use of a GUID for dfl devices. Device drivers may match
on type id and feature id, on the GUID, or on a combination of the type id,
feature id and GUID.
If the feature id and GUID are both non-zero, then the modalias string is:
"dfl:t0000f0009g{03020100-0504-0706-0809-0A0B0C0D0E0F}*"
If the feature id is zero and the GUID is non-zero, then the string is:
"dfl:t*f*g{03020100-0504-0706-0809-0A0B0C0D0E0F}*"
If the feature id is non-zero and the GUID is zero, then the string is
"dfl:t0000f0009*"
Followed the concept of the wmi device ID to define the GUID in string
format and reuse the existing GUID infrastructure.
Signed-off-by: Basheer Ahmed Muddebihal <[email protected]>
This patch introduces changes to enhance the identification and matching of features in the Device Feature List (DFL) using GUID (Globally Unique Identifier). The use of GUID allows for an infinite pool of feature IDs, and decentralized allocation, and enables the matching of DFL devices with their respective drivers based on GUID. This mechanism allows customers to match their custom IP with the desired or required driver. Changes made in this patch: 1. Modified the UEVENT string to reflect GUID matching, ensuring compatibility with the updated identification method. 2. Added system entries to display the GUID in Little Endian format, facilitating the interpretation of the GUID value. 3. Included wrapper functions for GUID matching and Feature ID matching, enabling the comparison and matching of GUIDs and feature. Signed-off-by: Basheer Ahmed Muddebihal <[email protected]>
Moving forward GUID match is the preferred match, UART is the first feature device that supports GUID, It provides a way to demonstrate and test the GUID match functionality. Signed-off-by: Basheer Ahmed Muddebihal <[email protected]>
With the introduction of GUIDs as DFL device identifiers, a DFL driver may be selected based on a GUID match or based on a type/feature ID match. A driver that matches based on GUID is written specifically for that device. A driver that matches based on type/feature ID is likely to be a more generalized driver that will support the device but may not enable all functionality. This change will prevent a DFL device from binding to a driver based on type/feature ID if a driver for the GUID is present in the system. Signed-off-by: Russ Weight <[email protected]> Signed-off-by: Basheer Ahmed Muddebihal <[email protected]>
This patch adds the DFL feature driver for the branch device feature which will bind using GUID, and processes the branch parameter to extract the address of the branch DFL, and branch DFL size to enumerate the devices present in the branch DFL. Signed-off-by: Basheer Ahmed Muddebihal <[email protected]>
Added sysfs entries for Group Id and Instance ID Signed-off-by: Basheer Ahmed Muddebihal <[email protected]>
The Device Feature List (DFL) defines a linked list of feature headers within the device MMIO space, offering an extensible method for adding features. Signed-off-by: Basheer Ahmed Muddebihal <[email protected]>
Processes the device tree interrupt entires and stores the two properties gic_arm_ref and fpga_intr_lines in to DFL dev strucure, these proerties are used to process the feature interrupt param block to register ISR. Signed-off-by: Basheer Ahmed Muddebihal <[email protected]>
The Intel SoCFPGA GSRD (Golden Software Reference Design) Yocto image
is by default built with CONFIG_FPGA=y (but CONFIG_FPGA_BRIDGE=m and
CONFIG_FPGA_REGION=m), which causes an unresolvable symbol conflict
between the kernel image and the fpga-mgr backport module.
Assuming that the kernel version is recent enough not to require any
updates to fpga-{mgr,bridge,region}, do not build these modules when
CONFIG_FPGA=y. Do not consider CONFIG_FPGA_BRIDGE and CONFIG_FPGA_REGION
to avoid a version mix between kernel-provided and backport modules.
This is not a complete solution and may result in unknown failures when
the builtin kernel modules are too old, but it does happen to work with
Intel SoCFPGA GSRD which is currently based on Linux 6.1.55 (LTS).
Link: https://github.com/altera-opensource/gsrd-socfpga
Link: https://github.com/altera-opensource/linux-socfpga
Signed-off-by: Peter Colberg <[email protected]>
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This is an early draft that adds support for embedded SoC FPGA, e.g., the GSRD for Agilex 7 F-Series Transceiver-SoC DevKit (P-Tile and E-Tile). The goal is to build against the unmodified linux-socfpga kernel as shipped with GSRD.
See corresponding Yocto layer in OFS/meta-ofs#14.