Update
- Updated the operator traversal method (
collect_numerics) for the faster scheduling. - Sorted the test directory (
tests) for the separated testing. - Support of the variable request buffer depth of AXIM-DMA controllers.
- Bug fix of
read_modify_write. - Bug fix of the stream stop condition (
source_stop->sink_stop) - Bug fix of
..._imm,reduce_...,argmax,argminoperators. - Bug fix of the address map assignment.
The required Veriloggen version is 2.3.0.
Environment
macOS 13.5.2 (Apple Silicon M2 Max)
- Python 3.10.6
- Icarus Verilog 12.0
- Pyverilog 1.3.0
- Veriloggen 2.3.0
- numpy 1.26.0rc1
- onnx 1.14.1
- torch 2.0.1
- torchvision 0.15.2
Ubuntu 20.04.6 (AMD Ryzen 9 5950X)
- Python 3.10.6
- Icarus Verilog 10.3
- Pyverilog 1.3.0
- Veriloggen 2.3.0
- numpy 1.26.0rc1
- onnx 1.14.1
- torch 2.0.1
- torchvision 0.15.2