First proper commit.

.gitattributes

@@ -0,0 +1,2 @@
+# Auto detect text files and perform LF normalization
+* text=auto

.gitignore

@@ -0,0 +1,44 @@
+# Cache files
+__pycache__/
+.pyc
+
+# Text editor remnants
+.vscode/
+.vs/
+.idea/
+CMakeLists.txt
+cmake-build-debug
+venv/
+
+# Project-specific ignores
+build/
+notes/
+baserom/
+*.elf
+*.sra
+*.z64
+*.map
+*.dump
+out.txt
+
+# Tool artifacts
+tools/ido7.1_compiler/*
+tools/overlayhelpers/batchdisasm/output/*
+tools/overlayhelpers/batchdisasm/output2/*
+tools/overlayhelpers/batchdisasm/mipsdisasm/*
+tools/disasm/output/*
+tools/asmsplitter/asm/*
+tools/asmsplitter/c/*
+
+# Assets
+*.rgba32.png
+*.rgb5a1.png
+*.i4.png
+*.i8.png
+*.ia4.png
+*.ia8.png
+*.ci4.png
+*.ci8.png
+
+#Per-user configuration
+.python-version

.gitmodules

@@ -0,0 +1,3 @@
+[submodule "tools/ZAP2"]
+	path = tools/ZAP2
+	url = https://github.com/NEstelami/ZAP2.git

README.md

@@ -1 +1,21 @@
-oot
+# Legend of Zelda: Ocarina of Time Master Quest (debug)
+
+```diff
+- WARNING! -
+
+The ROM this repository builds while has a matching checksum cannot be 'shifted' due
+to hardcoded pointers which have yet to be dumped. Thus this repository is currently
+in an experimental and research phase and cannot currently be used traditionally as a
+source code base for general changes.
+```
+
+This repo does not include all assets necessary for compiling the ROM. A prior copy of the game is required to extract the required assets.
+
+This is a disassembly and decompilation of Legend of Zelda: Ocarina of Time Master Quest (debug)
+
+It builds the following ROM:
+* zelda_ocarina_mq_dbg.z64 `md5: 717179476af84133b14ff73af87db57a`
+
+Please refer to the Getting Started guide in the Wiki for setup instructions.
+
+Thanks to z64me and CrookedPoe for their actor documentation. https://github.com/CrookedPoe/z64-rw

asm/__osDisableInt.s

@@ -0,0 +1,41 @@
+.include "macro.inc"
+
+# assembler directives
+.set noat      # allow manual use of $at
+.set noreorder # don't insert nops after branches
+.set gp=64     # allow use of 64-bit general purposee registers
+
+.section .text
+
+.align 4
+
+glabel __osDisableInt
+/* 007E80 80007280 3C0A8001 */  lui   $t2, %hi(__OSGlobalIntMask) # $t2, 0x8001
+/* 007E84 80007284 254AAD00 */  addiu $t2, %lo(__OSGlobalIntMask) # addiu $t2, $t2, -0x5300
+/* 007E88 80007288 8D4B0000 */  lw    $t3, ($t2)
+/* 007E8C 8000728C 316BFF00 */  andi  $t3, $t3, 0xff00
+/* 007E90 80007290 40086000 */  mfc0  $t0, $12
+/* 007E94 80007294 2401FFFE */  li    $at, -2
+/* 007E98 80007298 01014824 */  and   $t1, $t0, $at
+/* 007E9C 8000729C 40896000 */  mtc0  $t1, $12
+/* 007EA0 800072A0 31020001 */  andi  $v0, $t0, 1
+/* 007EA4 800072A4 8D480000 */  lw    $t0, ($t2)
+/* 007EA8 800072A8 3108FF00 */  andi  $t0, $t0, 0xff00
+/* 007EAC 800072AC 110B000E */  beq   $t0, $t3, .L800072E8
+/* 007EB0 800072B0 3C0A8001 */   lui   $t2, %hi(__osRunningThread) # $t2, 0x8001
+/* 007EB4 800072B4 254AAD50 */  addiu $t2, %lo(__osRunningThread) # addiu $t2, $t2, -0x52b0
+/* 007EB8 800072B8 8D490118 */  lw    $t1, 0x118($t2)
+/* 007EBC 800072BC 312AFF00 */  andi  $t2, $t1, 0xff00
+/* 007EC0 800072C0 01485024 */  and   $t2, $t2, $t0
+/* 007EC4 800072C4 3C01FFFF */  lui   $at, (0xFFFF00FF >> 16) # lui $at, 0xffff
+/* 007EC8 800072C8 342100FF */  ori   $at, (0xFFFF00FF & 0xFFFF) # ori $at, $at, 0xff
+/* 007ECC 800072CC 01214824 */  and   $t1, $t1, $at
+/* 007ED0 800072D0 012A4825 */  or    $t1, $t1, $t2
+/* 007ED4 800072D4 2401FFFE */  li    $at, -2
+/* 007ED8 800072D8 01214824 */  and   $t1, $t1, $at
+/* 007EDC 800072DC 40896000 */  mtc0  $t1, $12
+/* 007EE0 800072E0 00000000 */  nop   
+/* 007EE4 800072E4 00000000 */  nop   
+.L800072E8:
+/* 007EE8 800072E8 03E00008 */  jr    $ra
+/* 007EEC 800072EC 00000000 */   nop   

asm/__osGetCause.s

@@ -0,0 +1,15 @@
+.include "macro.inc"
+
+# assembler directives
+.set noat      # allow manual use of $at
+.set noreorder # don't insert nops after branches
+.set gp=64     # allow use of 64-bit general purposee registers
+
+.section .text
+
+.align 4
+
+glabel __osGetCause
+/* 008790 80007B90 40026800 */  mfc0  $v0, $13
+/* 008794 80007B94 03E00008 */  jr    $ra
+/* 008798 80007B98 00000000 */   nop   

asm/__osGetFpcCsr.s

@@ -0,0 +1,15 @@
+.include "macro.inc"
+
+# assembler directives
+.set noat      # allow manual use of $at
+.set noreorder # don't insert nops after branches
+.set gp=64     # allow use of 64-bit general purposee registers
+
+.section .text
+
+.align 4
+
+glabel __osGetFpcCsr
+/* 008680 80007A80 4442F800 */  cfc1  $v0, $31
+/* 008684 80007A84 03E00008 */  jr    $ra
+/* 008688 80007A88 00000000 */   nop   

asm/__osGetSR.s

@@ -0,0 +1,15 @@
+.include "macro.inc"
+
+# assembler directives
+.set noat      # allow manual use of $at
+.set noreorder # don't insert nops after branches
+.set gp=64     # allow use of 64-bit general purposee registers
+
+.section .text
+
+.align 4
+
+glabel __osGetSR
+/* 0052B0 800046B0 40026000 */  mfc0  $v0, $12
+/* 0052B4 800046B4 03E00008 */  jr    $ra
+/* 0052B8 800046B8 00000000 */   nop   

asm/__osProbeTLB.s

@@ -0,0 +1,62 @@
+.include "macro.inc"
+
+# assembler directives
+.set noat      # allow manual use of $at
+.set noreorder # don't insert nops after branches
+.set gp=64     # allow use of 64-bit general purposee registers
+
+.section .text
+
+.align 4
+
+glabel __osProbeTLB
+/* 005C40 80005040 40085000 */  mfc0  $t0, $10
+/* 005C44 80005044 310900FF */  andi  $t1, $t0, 0xff
+/* 005C48 80005048 2401E000 */  li    $at, -8192
+/* 005C4C 8000504C 00815024 */  and   $t2, $a0, $at
+/* 005C50 80005050 012A4825 */  or    $t1, $t1, $t2
+/* 005C54 80005054 40895000 */  mtc0  $t1, $10
+/* 005C58 80005058 00000000 */  nop   
+/* 005C5C 8000505C 00000000 */  nop   
+/* 005C60 80005060 00000000 */  nop   
+/* 005C64 80005064 42000008 */  tlbp  
+/* 005C68 80005068 00000000 */  nop   
+/* 005C6C 8000506C 00000000 */  nop   
+/* 005C70 80005070 400B0000 */  mfc0  $t3, $0
+/* 005C74 80005074 3C018000 */  lui   $at, 0x8000
+/* 005C78 80005078 01615824 */  and   $t3, $t3, $at
+/* 005C7C 8000507C 1560001A */  bnez  $t3, .L800050E8
+/* 005C80 80005080 00000000 */   nop   
+/* 005C84 80005084 42000001 */  tlbr  
+/* 005C88 80005088 00000000 */  nop   
+/* 005C8C 8000508C 00000000 */  nop   
+/* 005C90 80005090 00000000 */  nop   
+/* 005C94 80005094 400B2800 */  mfc0  $t3, $5
+/* 005C98 80005098 216B2000 */  addi  $t3, $t3, 0x2000
+/* 005C9C 8000509C 000B5842 */  srl   $t3, $t3, 1
+/* 005CA0 800050A0 01646024 */  and   $t4, $t3, $a0
+/* 005CA4 800050A4 15800004 */  bnez  $t4, .L800050B8
+/* 005CA8 800050A8 216BFFFF */   addi  $t3, $t3, -1
+/* 005CAC 800050AC 40021000 */  mfc0  $v0, $2
+/* 005CB0 800050B0 10000002 */  b     .L800050BC
+/* 005CB4 800050B4 00000000 */   nop   
+.L800050B8:
+/* 005CB8 800050B8 40021800 */  mfc0  $v0, $3
+.L800050BC:
+/* 005CBC 800050BC 304D0002 */  andi  $t5, $v0, 2
+/* 005CC0 800050C0 11A00009 */  beqz  $t5, .L800050E8
+/* 005CC4 800050C4 00000000 */   nop   
+/* 005CC8 800050C8 3C013FFF */  lui   $at, (0x3FFFFFC0 >> 16) # lui $at, 0x3fff
+/* 005CCC 800050CC 3421FFC0 */  ori   $at, (0x3FFFFFC0 & 0xFFFF) # ori $at, $at, 0xffc0
+/* 005CD0 800050D0 00411024 */  and   $v0, $v0, $at
+/* 005CD4 800050D4 00021180 */  sll   $v0, $v0, 6
+/* 005CD8 800050D8 008B6824 */  and   $t5, $a0, $t3
+/* 005CDC 800050DC 004D1020 */  add   $v0, $v0, $t5
+/* 005CE0 800050E0 10000002 */  b     .L800050EC
+/* 005CE4 800050E4 00000000 */   nop   
+.L800050E8:
+/* 005CE8 800050E8 2402FFFF */  li    $v0, -1
+.L800050EC:
+/* 005CEC 800050EC 40885000 */  mtc0  $t0, $10
+/* 005CF0 800050F0 03E00008 */  jr    $ra
+/* 005CF4 800050F4 00000000 */   nop   

asm/__osRestoreInt.s

@@ -0,0 +1,19 @@
+.include "macro.inc"
+
+# assembler directives
+.set noat      # allow manual use of $at
+.set noreorder # don't insert nops after branches
+.set gp=64     # allow use of 64-bit general purposee registers
+
+.section .text
+
+.align 4
+
+glabel __osRestoreInt
+/* 007EF0 800072F0 40086000 */  mfc0  $t0, $12
+/* 007EF4 800072F4 01044025 */  or    $t0, $t0, $a0
+/* 007EF8 800072F8 40886000 */  mtc0  $t0, $12
+/* 007EFC 800072FC 00000000 */  nop   
+/* 007F00 80007300 00000000 */  nop   
+/* 007F04 80007304 03E00008 */  jr    $ra
+/* 007F08 80007308 00000000 */   nop   

asm/__osSetCompare.s

@@ -0,0 +1,15 @@
+.include "macro.inc"
+
+# assembler directives
+.set noat      # allow manual use of $at
+.set noreorder # don't insert nops after branches
+.set gp=64     # allow use of 64-bit general purposee registers
+
+.section .text
+
+.align 4
+
+glabel __osSetCompare
+/* 007B00 80006F00 40845800 */  mtc0  $a0, $11
+/* 007B04 80006F04 03E00008 */  jr    $ra
+/* 007B08 80006F08 00000000 */   nop   

asm/__osSetFpcCsr.s

@@ -0,0 +1,16 @@
+.include "macro.inc"
+
+# assembler directives
+.set noat      # allow manual use of $at
+.set noreorder # don't insert nops after branches
+.set gp=64     # allow use of 64-bit general purposee registers
+
+.section .text
+
+.align 4
+
+glabel __osSetFpcCsr
+/* 008670 80007A70 4442F800 */  cfc1  $v0, $31
+/* 008674 80007A74 44C4F800 */  ctc1  $a0, $31
+/* 008678 80007A78 03E00008 */  jr    $ra
+/* 00867C 80007A7C 00000000 */   nop   

asm/__osSetSR.s

@@ -0,0 +1,16 @@
+.include "macro.inc"
+
+# assembler directives
+.set noat      # allow manual use of $at
+.set noreorder # don't insert nops after branches
+.set gp=64     # allow use of 64-bit general purposee registers
+
+.section .text
+
+.align 4
+
+glabel __osSetSR
+/* 0052A0 800046A0 40846000 */  mtc0  $a0, $12
+/* 0052A4 800046A4 00000000 */  nop   
+/* 0052A8 800046A8 03E00008 */  jr    $ra
+/* 0052AC 800046AC 00000000 */   nop   

asm/__osSetWatchLo.s

@@ -0,0 +1,16 @@
+.include "macro.inc"
+
+# assembler directives
+.set noat      # allow manual use of $at
+.set noreorder # don't insert nops after branches
+.set gp=64     # allow use of 64-bit general purposee registers
+
+.section .text
+
+.align 4
+
+glabel __osSetWatchLo
+/* 009F10 80009310 40849000 */  mtc0  $a0, $18
+/* 009F14 80009314 00000000 */  nop   
+/* 009F18 80009318 03E00008 */  jr    $ra
+/* 009F1C 8000931C 00000000 */   nop