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1. SoC_2024 SoC_2024 Public

   This is my 2nd project, where I connect my RISC core to an UART Interface through APB3 bus.

   Verilog

2. Audio_Equalizer_2024 Audio_Equalizer_2024 Public

   This is a final project of the class "DSP on FPGA" where I work with FIR/IIR filter, CODEC on DE10-Standard.

   MATLAB