RUN_BUILD --> Fix visibiliy of clock on remove or connecting wires

FPGAwars · Jan 10, 2025 · 4c8b801 · 4c8b801
1 parent 187e0b8
commit 4c8b801
Showing 1 changed file with 3 additions and 2 deletions.
diff --git a/build.info b/build.info
@@ -3,8 +3,9 @@
 Type: WIP
 App Changes: 
 
-  - Fix non visible clk in block insertion
-  - Fix not showing wires bifurcations marks.
+  - Fix non visible clk in wire remove or attach action by @cavearr
+  - Fix non visible clk in block insertion by @cavearr
+  - Fix not showing wires bifurcations marks by @cavearr
   - Add .ice files opened with double click from file manager to  recent files option by @lmcapacho
   - Accuracy selection and click on items (now is pixel-perfect click and selections) by @cavearr 
   - Speed up UI/load-flow by @cavearr