Skip to content

Commit

Permalink
[RISCV] Decompose locally repeating shuffles (without exact VLEN) (ll…
Browse files Browse the repository at this point in the history 
…vm#125735)

High LMUL shuffles are expensive on typical SIMD implementations.
Without exact vector length knowledge, we struggle to map elements
within the vector to the register within the vector register group.
However, there are some patterns where we can perform a vector length
agnostic (VLA) shuffle by leveraging knowledge of the pattern performed
even without the ability to map individual elements to registers. An
existing in tree example is vector reverse.

This patch introduces another such case. Specifically, if we have a
shuffle where the a local rearrangement of elements is happening within
a 128b (really zvlNb) chunk, and we're applying the same pattern to each
chunk, we can decompose a high LMUL shuffle into a linear number of m1
shuffles. We take advantage of the fact the tail of the operation is
undefined, and repeat the pattern for all elements in the source
register group - not just the ones the fixed vector type covers.

This is an optimization for typical SIMD vrgather designs, but could be
a pessimation on hardware for which vrgather's execution cost is not
independent of the runtime VL.
  • Loading branch information
@preames
preames authored Feb 5, 2025
1 parent fc4210f commit 6b3cbf2
Show file tree
Hide file tree
Showing 3 changed files with 236 additions and 75 deletions.
56 changes: 52 additions & 4 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5325,6 +5325,21 @@ static SDValue lowerDisjointIndicesShuffle(ShuffleVectorSDNode *SVN,
return DAG.getVectorShuffle(VT, DL, Select, DAG.getUNDEF(VT), NewMask);
}

/// Is this mask local (i.e. elements only move within their local span), and
/// repeating (that is, the same rearrangement is being done within each span)?
static bool isLocalRepeatingShuffle(ArrayRef<int> Mask, int Span) {
// TODO: Could improve the case where undef elements exist in the first span.
for (auto [I, M] : enumerate(Mask)) {
if (M == -1)
continue;
int ChunkLo = I - (I % Span);
int ChunkHi = ChunkLo + Span;
if (M < ChunkLo || M >= ChunkHi || M - ChunkLo != Mask[I % Span])
return false;
}
return true;
}

/// Try to widen element type to get a new mask value for a better permutation
/// sequence. This doesn't try to inspect the widened mask for profitability;
/// we speculate the widened form is equal or better. This has the effect of
Expand Down Expand Up @@ -5686,10 +5701,43 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
: DAG.getUNDEF(XLenVT));
}
SDValue LHSIndices = DAG.getBuildVector(IndexVT, DL, GatherIndicesLHS);
LHSIndices = convertToScalableVector(IndexContainerVT, LHSIndices, DAG,
Subtarget);
SDValue Gather = DAG.getNode(GatherVVOpc, DL, ContainerVT, V1, LHSIndices,
DAG.getUNDEF(ContainerVT), TrueMask, VL);
LHSIndices =
convertToScalableVector(IndexContainerVT, LHSIndices, DAG, Subtarget);

SDValue Gather;
// If we have a locally repeating mask, then we can reuse the first register
// in the index register group for all registers within the source register
// group. TODO: This generalizes to m2, and m4. Also, this is currently
// picking up cases with a fully undef tail which could be more directly
// handled with fewer redundant vrgathers
const MVT M1VT = getLMUL1VT(ContainerVT);
auto VLMAX = RISCVTargetLowering::computeVLMAXBounds(M1VT, Subtarget).first;
if (ContainerVT.bitsGT(M1VT) && isLocalRepeatingShuffle(Mask, VLMAX)) {
EVT SubIndexVT = M1VT.changeVectorElementType(IndexVT.getScalarType());
SDValue SubIndex =
DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubIndexVT, LHSIndices,
DAG.getVectorIdxConstant(0, DL));
auto [InnerTrueMask, InnerVL] =
getDefaultScalableVLOps(M1VT, DL, DAG, Subtarget);
int N = ContainerVT.getVectorMinNumElements() /
M1VT.getVectorMinNumElements();
assert(isPowerOf2_32(N) && N <= 8);
Gather = DAG.getUNDEF(ContainerVT);
for (int i = 0; i < N; i++) {
SDValue SubIdx =
DAG.getVectorIdxConstant(M1VT.getVectorMinNumElements() * i, DL);
SDValue SubV1 =
DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, M1VT, V1, SubIdx);
SDValue SubVec =
DAG.getNode(GatherVVOpc, DL, M1VT, SubV1, SubIndex,
DAG.getUNDEF(M1VT), InnerTrueMask, InnerVL);
Gather = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ContainerVT, Gather,
SubVec, SubIdx);
}
} else {
Gather = DAG.getNode(GatherVVOpc, DL, ContainerVT, V1, LHSIndices,
DAG.getUNDEF(ContainerVT), TrueMask, VL);
}
return convertFromScalableVector(VT, Gather, DAG, Subtarget);
}

Expand Down
131 changes: 72 additions & 59 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -874,27 +874,30 @@ define <16 x i8> @reverse_v16i8_2(<8 x i8> %a, <8 x i8> %b) {
define <32 x i8> @reverse_v32i8_2(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: reverse_v32i8_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: vid.v v12
; CHECK-NEXT: addi a1, a0, -1
; CHECK-NEXT: vrsub.vx v12, v12, a1
; CHECK-NEXT: lui a1, 16
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT: vid.v v10
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: addi a2, a0, -1
; CHECK-NEXT: vrsub.vx v10, v10, a2
; CHECK-NEXT: lui a2, 16
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT: vrgatherei16.vv v15, v8, v12
; CHECK-NEXT: vrgatherei16.vv v14, v9, v12
; CHECK-NEXT: vrgatherei16.vv v15, v8, v10
; CHECK-NEXT: vrgatherei16.vv v14, v12, v10
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-NEXT: vid.v v10
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: vrsub.vi v10, v10, 15
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; CHECK-NEXT: vrgather.vv v17, v13, v10
; CHECK-NEXT: vrgather.vv v16, v9, v10
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vmv.s.x v0, a2
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: addi a0, a0, -32
; CHECK-NEXT: vrsub.vi v12, v8, 15
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v14, a0
; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: ret
%res = shufflevector <16 x i8> %a, <16 x i8> %b, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <32 x i8> %res
Expand Down Expand Up @@ -943,23 +946,25 @@ define <8 x i16> @reverse_v8i16_2(<4 x i16> %a, <4 x i16> %b) {
define <16 x i16> @reverse_v16i16_2(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: reverse_v16i16_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vid.v v10
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: vrsub.vi v10, v10, 7
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vrgather.vv v13, v12, v10
; CHECK-NEXT: vrgather.vv v12, v9, v10
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: srli a1, a0, 1
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: vrsub.vx v9, v9, a1
; CHECK-NEXT: vrgather.vv v13, v8, v9
; CHECK-NEXT: vrgather.vv v12, v11, v9
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: li a1, 255
; CHECK-NEXT: addi a0, a0, -16
; CHECK-NEXT: vrsub.vi v14, v8, 7
; CHECK-NEXT: vrgather.vv v15, v8, v9
; CHECK-NEXT: vrgather.vv v14, v10, v9
; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: vslidedown.vx v8, v12, a0
; CHECK-NEXT: vrgather.vv v8, v10, v14, v0.t
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v14, a0
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret
%res = shufflevector <8 x i16> %a, <8 x i16> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <16 x i16> %res
Expand Down Expand Up @@ -1024,24 +1029,27 @@ define <4 x i32> @reverse_v4i32_2(<2 x i32> %a, < 2 x i32> %b) {
define <8 x i32> @reverse_v8i32_2(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: reverse_v8i32_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vid.v v10
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: srli a1, a0, 2
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: vrsub.vx v9, v9, a1
; CHECK-NEXT: vrgather.vv v13, v8, v9
; CHECK-NEXT: vrgather.vv v12, v11, v9
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vid.v v12
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vmv.v.i v0, 15
; CHECK-NEXT: vrsub.vi v10, v10, 3
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vrgatherei16.vv v15, v11, v10
; CHECK-NEXT: vrgatherei16.vv v14, v9, v10
; CHECK-NEXT: srli a1, a0, 2
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: vrsub.vi v14, v8, 3
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: addi a0, a0, -8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; CHECK-NEXT: vrsub.vx v10, v12, a1
; CHECK-NEXT: vrgather.vv v13, v8, v10
; CHECK-NEXT: vrgather.vv v12, v9, v10
; CHECK-NEXT: vmv.v.i v0, 15
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v12, a0
; CHECK-NEXT: vrgatherei16.vv v8, v10, v14, v0.t
; CHECK-NEXT: vmerge.vvm v8, v8, v14, v0
; CHECK-NEXT: ret
%res = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x i32> %res
Expand Down Expand Up @@ -1197,23 +1205,25 @@ define <8 x half> @reverse_v8f16_2(<4 x half> %a, <4 x half> %b) {
define <16 x half> @reverse_v16f16_2(<8 x half> %a, <8 x half> %b) {
; CHECK-LABEL: reverse_v16f16_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vid.v v10
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: vrsub.vi v10, v10, 7
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vrgather.vv v13, v12, v10
; CHECK-NEXT: vrgather.vv v12, v9, v10
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: srli a1, a0, 1
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: vrsub.vx v9, v9, a1
; CHECK-NEXT: vrgather.vv v13, v8, v9
; CHECK-NEXT: vrgather.vv v12, v11, v9
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: li a1, 255
; CHECK-NEXT: addi a0, a0, -16
; CHECK-NEXT: vrsub.vi v14, v8, 7
; CHECK-NEXT: vrgather.vv v15, v8, v9
; CHECK-NEXT: vrgather.vv v14, v10, v9
; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: vslidedown.vx v8, v12, a0
; CHECK-NEXT: vrgather.vv v8, v10, v14, v0.t
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v14, a0
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret
%res = shufflevector <8 x half> %a, <8 x half> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <16 x half> %res
Expand Down Expand Up @@ -1269,24 +1279,27 @@ define <4 x float> @reverse_v4f32_2(<2 x float> %a, <2 x float> %b) {
define <8 x float> @reverse_v8f32_2(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: reverse_v8f32_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vid.v v10
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: srli a1, a0, 2
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: vrsub.vx v9, v9, a1
; CHECK-NEXT: vrgather.vv v13, v8, v9
; CHECK-NEXT: vrgather.vv v12, v11, v9
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vid.v v12
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vmv.v.i v0, 15
; CHECK-NEXT: vrsub.vi v10, v10, 3
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vrgatherei16.vv v15, v11, v10
; CHECK-NEXT: vrgatherei16.vv v14, v9, v10
; CHECK-NEXT: srli a1, a0, 2
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: vrsub.vi v14, v8, 3
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: addi a0, a0, -8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; CHECK-NEXT: vrsub.vx v10, v12, a1
; CHECK-NEXT: vrgather.vv v13, v8, v10
; CHECK-NEXT: vrgather.vv v12, v9, v10
; CHECK-NEXT: vmv.v.i v0, 15
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v12, a0
; CHECK-NEXT: vrgatherei16.vv v8, v10, v14, v0.t
; CHECK-NEXT: vmerge.vvm v8, v8, v14, v0
; CHECK-NEXT: ret
%res = shufflevector <4 x float> %a, <4 x float> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x float> %res
Expand Down
Loading

0 comments on commit 6b3cbf2

Please sign in to comment.