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Update e3smv3 pgn and tsc tests with L80 ICs for atm and lnd #4513

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Feb 16, 2024
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6 changes: 3 additions & 3 deletions CIME/SystemTests/pgn.py
Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,7 @@
]
)
FCLD_NC = "cam.h0.cloud.nc"
INIT_COND_FILE_TEMPLATE = "20210915.v2.ne4_oQU240.F2010.{}.{}.0002-{:02d}-01-00000.nc"
INIT_COND_FILE_TEMPLATE = "20231105.v3b01.F2010.ne4_oQU240.chrysalis.{}.{}.0002-{:02d}-01-00000.nc"
INSTANCE_FILE_TEMPLATE = "{}{}_{:04d}.h0.0001-01-01-00000{}.nc"


Expand Down Expand Up @@ -95,8 +95,8 @@ def build_phase(self, sharedlib_only=False, model_only=False):
logger.debug("PGN_INFO: Updating user_nl_* files")

csmdata_root = self._case.get_value("DIN_LOC_ROOT")
csmdata_atm = os.path.join(csmdata_root, "atm/cam/inic/homme/ne4_v2_init")
csmdata_lnd = os.path.join(csmdata_root, "lnd/clm2/initdata/ne4_oQU240_v2_init")
csmdata_atm = os.path.join(csmdata_root, "atm/cam/inic/homme/ne4_v3_init")
csmdata_lnd = os.path.join(csmdata_root, "lnd/clm2/initdata/ne4_oQU240_v3_init")

iinst = 1
for icond in range(1, NUMBER_INITIAL_CONDITIONS + 1):
Expand Down
6 changes: 3 additions & 3 deletions CIME/SystemTests/tsc.py
Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@
SIM_LENGTH = 600 # seconds
OUT_FREQ = 10 # seconds
INSPECT_AT = [300, 450, 600] # seconds
INIT_COND_FILE_TEMPLATE = "20210915.v2.ne4_oQU240.F2010.{}.{}.0002-{:02d}-01-00000.nc"
INIT_COND_FILE_TEMPLATE = "20231105.v3b01.F2010.ne4_oQU240.chrysalis.{}.{}.0002-{:02d}-01-00000.nc"
VAR_LIST = [
"T",
"Q",
Expand Down Expand Up @@ -100,8 +100,8 @@ def _run_with_specified_dtime(self, dtime=2):
self._case.set_value("STOP_OPTION", "nsteps")

csmdata_root = self._case.get_value("DIN_LOC_ROOT")
csmdata_atm = os.path.join(csmdata_root, "atm/cam/inic/homme/ne4_v2_init")
csmdata_lnd = os.path.join(csmdata_root, "lnd/clm2/initdata/ne4_oQU240_v2_init")
csmdata_atm = os.path.join(csmdata_root, "atm/cam/inic/homme/ne4_v3_init")
csmdata_lnd = os.path.join(csmdata_root, "lnd/clm2/initdata/ne4_oQU240_v3_init")

nstep_output = OUT_FREQ // dtime
for iinst in range(1, NINST + 1):
Expand Down
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