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RISC-V: Support VLS basic operation auto-vectorization
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This patch support VLS modes auto-vectorization to enhance VLA auto-vectorization
when niters is known.

Consider this following case:

  void __attribute__ ((noinline, noclone))                                     \
  PREFIX##_##TYPE##NUM (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c)  \
  {                                                                            \
    for (int i = 0; i < NUM; ++i)                                              \
      a[i] = b[i] OP c[i];                                                     \
  }

DEF_OP_VV (plus, 16, int8_t, +)

Before this patch:

plus_int8_t16(signed char*, signed char*, signed char*):
        li      a5,16
        csrr    a4,vlenb
        bleu    a5,a4,.L2
        mv      a5,a4
.L2:
        vsetvli zero,a5,e8,m1,ta,ma
        vle8.v  v2,0(a1)
        vle8.v  v1,0(a2)
        vsetvli a4,zero,e8,m1,ta,ma
        vadd.vv v1,v1,v2
        vsetvli zero,a5,e8,m1,ta,ma
        vse8.v  v1,0(a0)
        ret

After this patch:

plus_int8_t16:
	vsetivli	zero,16,e8,m1,ta,ma
	vle8.v	v1,0(a2)
	vle8.v	v2,0(a1)
	vadd.vv	v1,v1,v2
	vse8.v	v1,0(a0)
	ret

gcc/ChangeLog:

	* config/riscv/autovec-vls.md (<optab><mode>3): Add VLS modes.
	* config/riscv/vector-iterators.md: Ditto.
	* config/riscv/vector.md: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls/def.h: Add basic operations.
	* gcc.target/riscv/rvv/autovec/vls/and-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/and-2.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/and-3.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/div-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/ior-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/ior-2.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/ior-3.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/max-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/min-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/minus-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/minus-2.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/minus-3.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/mod-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/mult-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/plus-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/plus-2.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/plus-3.c: New test.
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@zhongjuzhe @Incarnation-p-lee
zhongjuzhe authored and Incarnation-p-lee committed Aug 7, 2023
1 parent bb3ceeb commit 9cba4fc
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Showing 21 changed files with 1,217 additions and 83 deletions.
23 changes: 23 additions & 0 deletions gcc/config/riscv/autovec-vls.md
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Original file line number Diff line number Diff line change
Expand Up @@ -158,3 +158,26 @@
DONE;
}
)

;; -------------------------------------------------------------------------
;; ---- [INT] Binary operations
;; -------------------------------------------------------------------------
;; Includes:
;; - vadd.vv/vsub.vv/...
;; - vadd.vi/vsub.vi/...
;; -------------------------------------------------------------------------

(define_insn_and_split "<optab><mode>3"
[(set (match_operand:VLSI 0 "register_operand")
(any_int_binop_no_shift:VLSI
(match_operand:VLSI 1 "<binop_rhs1_predicate>")
(match_operand:VLSI 2 "<binop_rhs2_predicate>")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
{
riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
riscv_vector::RVV_BINOP, operands);
DONE;
})
93 changes: 93 additions & 0 deletions gcc/config/riscv/vector-iterators.md
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Original file line number Diff line number Diff line change
Expand Up @@ -543,6 +543,51 @@
RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
])

(define_mode_iterator V_VLSI_QHS [
RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")

RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")

RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")

(V1QI "TARGET_VECTOR_VLS")
(V2QI "TARGET_VECTOR_VLS")
(V4QI "TARGET_VECTOR_VLS")
(V8QI "TARGET_VECTOR_VLS")
(V16QI "TARGET_VECTOR_VLS")
(V32QI "TARGET_VECTOR_VLS")
(V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
(V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
(V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
(V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
(V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
(V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
(V4096QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
(V1HI "TARGET_VECTOR_VLS")
(V2HI "TARGET_VECTOR_VLS")
(V4HI "TARGET_VECTOR_VLS")
(V8HI "TARGET_VECTOR_VLS")
(V16HI "TARGET_VECTOR_VLS")
(V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
(V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
(V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
(V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
(V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
(V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
(V2048HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
(V1SI "TARGET_VECTOR_VLS")
(V2SI "TARGET_VECTOR_VLS")
(V4SI "TARGET_VECTOR_VLS")
(V8SI "TARGET_VECTOR_VLS")
(V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
(V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
(V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
(V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
(V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
(V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
(V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
])

(define_mode_iterator VI_D [
(RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
(RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
Expand Down Expand Up @@ -2292,3 +2337,51 @@
(V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
(V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
(V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")])

(define_mode_iterator VLSI [
(V1QI "TARGET_VECTOR_VLS")
(V2QI "TARGET_VECTOR_VLS")
(V4QI "TARGET_VECTOR_VLS")
(V8QI "TARGET_VECTOR_VLS")
(V16QI "TARGET_VECTOR_VLS")
(V32QI "TARGET_VECTOR_VLS")
(V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
(V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
(V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
(V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
(V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
(V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
(V4096QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
(V1HI "TARGET_VECTOR_VLS")
(V2HI "TARGET_VECTOR_VLS")
(V4HI "TARGET_VECTOR_VLS")
(V8HI "TARGET_VECTOR_VLS")
(V16HI "TARGET_VECTOR_VLS")
(V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
(V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
(V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
(V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
(V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
(V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
(V2048HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
(V1SI "TARGET_VECTOR_VLS")
(V2SI "TARGET_VECTOR_VLS")
(V4SI "TARGET_VECTOR_VLS")
(V8SI "TARGET_VECTOR_VLS")
(V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
(V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
(V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
(V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
(V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
(V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
(V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
(V1DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
(V2DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
(V4DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
(V8DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64")
(V16DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
(V32DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256")
(V64DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512")
(V128DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024")
(V256DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048")
(V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")])
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