i#3544 RV64: Rebase the dcontext pointer.

core/arch/arch_exports.h

@@ -1,6 +1,7 @@
 /* **********************************************************
  * Copyright (c) 2011-2022 Google, Inc.  All rights reserved.
  * Copyright (c) 2000-2010 VMware, Inc.  All rights reserved.
+ * Copyright (c) 2025 Foundation of Research and Technology, Hellas.
  * **********************************************************/
 
 /*
@@ -1819,4 +1820,15 @@ typedef struct _rseq_entry_state_t {
 } rseq_entry_state_t;
 #endif
 
+/*
+ * In riscv we cannot address the entire dcontext by using base + immediate.
+ * for the reason we add 0x800 to the saved pointer and access it by
+ * substracting 0x800 from the offset in the struct.
+ */
+#ifdef RISCV64
+#    define CONTEXT_REBASE_OFFT 0x800
+#else
+#    define CONTEXT_REBASE_OFFT 0
+#endif
+
 #endif /* _ARCH_EXPORTS_H_ */

core/arch/emit_utils_shared.c

@@ -1,6 +1,7 @@
 /* **********************************************************
  * Copyright (c) 2010-2022 Google, Inc.  All rights reserved.
  * Copyright (c) 2000-2010 VMware, Inc.  All rights reserved.
+ * Copyright (c) 2025 Foundation of Research and Technology, Hellas.
  * **********************************************************/
 
 /*
@@ -2180,12 +2181,14 @@ emit_fcache_enter_common(dcontext_t *dcontext, generated_code_t *code, byte *pc,
 #elif defined(RISCV64)
     APP(&ilist,
         INSTR_CREATE_ld(dcontext, opnd_create_reg(DR_REG_A0),
-                        opnd_create_base_disp(REG_DCXT, DR_REG_NULL, 0,
-                                              REG_OFFSET(DR_REG_A0), OPSZ_8)));
+                        opnd_create_base_disp(
+                            REG_DCXT, DR_REG_NULL, 0,
+                            (int)REG_OFFSET(DR_REG_A0) - CONTEXT_REBASE_OFFT, OPSZ_8)));
     APP(&ilist,
         INSTR_CREATE_ld(dcontext, opnd_create_reg(DR_REG_A1),
-                        opnd_create_base_disp(REG_DCXT, DR_REG_NULL, 0,
-                                              REG_OFFSET(DR_REG_A1), OPSZ_8)));
+                        opnd_create_base_disp(
+                            REG_DCXT, DR_REG_NULL, 0,
+                            (int)REG_OFFSET(DR_REG_A1) - CONTEXT_REBASE_OFFT, OPSZ_8)));
 
     APP(&ilist,
         INSTR_CREATE_sd(
@@ -2380,9 +2383,31 @@ append_call_dispatch(dcontext_t *dcontext, instrlist_t *ilist, bool absolute)
     /* call central d_r_dispatch routine */
     /* for x64 linux we could optimize and avoid the "mov rdi, rdi" */
     /* for ARM we use _noreturn to avoid storing to %lr */
+
+    /*
+     * REG_DCTXT holds the rebased dcontext d_r_dispatch expect the normal one
+     * so we should restore it.
+     *
+     * Currently only affects RISCV64
+     */
+#if (CONTEXT_REBASE_OFFT != 0)
+    if (absolute) {
+        dr_insert_call_noreturn((void *)dcontext, ilist, NULL /*append*/,
+                                (void *)d_r_dispatch, 1,
+                                OPND_CREATE_INTPTR((ptr_int_t)dcontext));
+    } else {
+        APP(ilist,
+            XINST_CREATE_add_2src(dcontext, opnd_create_reg(DR_REG_A0),
+                                  opnd_create_reg(REG_DCTXT),
+                                  OPND_CREATE_INT32(-CONTEXT_REBASE_OFFT)));
+        dr_insert_call_noreturn((void *)dcontext, ilist, NULL /*append*/,
+                                (void *)d_r_dispatch, 1, opnd_create_reg(DR_REG_A0));
+    }
+#else
     dr_insert_call_noreturn(
         (void *)dcontext, ilist, NULL /*append*/, (void *)d_r_dispatch, 1,
         absolute ? OPND_CREATE_INTPTR((ptr_int_t)dcontext) : opnd_create_reg(REG_DCTXT));
+#endif
 
     /* d_r_dispatch() shouldn't return! */
     insert_reachable_cti(dcontext, ilist, NULL, vmcode_get_start(),

core/arch/mangle_shared.c

@@ -2,6 +2,7 @@
  * Copyright (c) 2010-2022 Google, Inc.  All rights reserved.
  * Copyright (c) 2010 Massachusetts Institute of Technology  All rights reserved.
  * Copyright (c) 2000-2010 VMware, Inc.  All rights reserved.
+ * Copyright (c) 2025 Foundation of Research and Technology, Hellas.
  * ******************************************************************************/
 
 /*
@@ -81,6 +82,9 @@ get_clean_call_temp_stack_size(void)
 /* utility routines for inserting clean calls to an instrumentation routine
  * strategy is very similar to fcache_enter/return
  * FIXME: try to share code with fcache_enter/return?
+ * FIXME: Return the correct mcontext base when CONTEXT_REBASE_OFFT is used
+ * This will need calls like opnd_create_dcontext_field_via_reg_sz to be replaced
+ * with something else. Currently we work around that by other means.
  *
  * first swap stacks to DynamoRIO stack:
  *      SAVE_TO_UPCONTEXT %xsp,xsp_OFFSET
@@ -757,7 +761,8 @@ insert_meta_call_vargs(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr,
              * We save it to dcontext.mcontext.x0.
              */
             PRE(ilist, instr,
-                XINST_CREATE_store(dcontext, OPND_CREATE_MEMPTR(link_reg, 0),
+                XINST_CREATE_store(dcontext,
+                                   OPND_CREATE_MEMPTR(link_reg, -CONTEXT_REBASE_OFFT),
                                    opnd_create_reg(SCRATCH_REG0)));
             instrlist_insert_mov_immed_ptrsz(dcontext, (ptr_int_t)DR_WHERE_CLEAN_CALLEE,
                                              opnd_create_reg(SCRATCH_REG0), ilist, instr,
@@ -770,7 +775,7 @@ insert_meta_call_vargs(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr,
             /* Restore scratch_reg from dcontext.mcontext.x0. */
             PRE(ilist, instr,
                 XINST_CREATE_load(dcontext, opnd_create_reg(SCRATCH_REG0),
-                                  OPND_CREATE_MEMPTR(link_reg, 0)));
+                                  OPND_CREATE_MEMPTR(link_reg, -CONTEXT_REBASE_OFFT)));
 #else
             /* SCRATCH_REG0 is dead here, because clean calls only support "cdecl",
              * which specifies that the caller must save xax (and xcx and xdx).
@@ -823,7 +828,8 @@ insert_meta_call_vargs(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr,
              * We save it to dcontext.mcontext.x0.
              */
             PRE(ilist, instr,
-                XINST_CREATE_store(dcontext, OPND_CREATE_MEMPTR(SCRATCH_REG0, 0),
+                XINST_CREATE_store(dcontext,
+                                   OPND_CREATE_MEMPTR(SCRATCH_REG0, -CONTEXT_REBASE_OFFT),
                                    opnd_create_reg(SCRATCH_REG1)));
             instrlist_insert_mov_immed_ptrsz(dcontext, (ptr_int_t)whereami,
                                              opnd_create_reg(SCRATCH_REG1), ilist, instr,
@@ -835,8 +841,9 @@ insert_meta_call_vargs(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr,
                     WHEREAMI_OFFSET));
             /* Restore scratch_reg from dcontext.mcontext.x0. */
             PRE(ilist, instr,
-                XINST_CREATE_load(dcontext, opnd_create_reg(SCRATCH_REG1),
-                                  OPND_CREATE_MEMPTR(SCRATCH_REG0, 0)));
+                XINST_CREATE_load(
+                    dcontext, opnd_create_reg(SCRATCH_REG1),
+                    OPND_CREATE_MEMPTR(SCRATCH_REG0, -CONTEXT_REBASE_OFFT)));
 #else
             PRE(ilist, instr,
                 instr_create_save_immed_to_dc_via_reg(dcontext, SCRATCH_REG0,

core/arch/riscv64/emit_utils.c

@@ -1,6 +1,6 @@
 /* **********************************************************
  * Copyright (c) 2022 Rivos, Inc.  All rights reserved.
- * Copyright (c) 2024 Foundation of Research and Technology, Hellas.
+ * Copyright (c) 2024-2025 Foundation of Research and Technology, Hellas.
  * **********************************************************/
 
 /*
@@ -698,12 +698,13 @@ append_restore_simd_reg(dcontext_t *dcontext, instrlist_t *ilist, bool absolute)
          *
          *           ma            ta         sew=8       lmul=8 */
         vtypei = (0b1 << 7) | (0b1 << 6) | (0b000 << 3) | 0b011;
-        memopnd = opnd_create_dcontext_field_via_reg_sz(
-            dcontext, DR_REG_A1, 0, reg_get_size_lmul(DR_REG_VR0, RV64_LMUL_8));
+        memopnd = opnd_create_base_disp(DR_REG_A1, REG_NULL, 0, 0,
+                                        reg_get_size_lmul(DR_REG_VR0, RV64_LMUL_8));
         APP(ilist,
-            INSTR_CREATE_addi(dcontext, opnd_create_reg(DR_REG_A1),
-                              opnd_create_reg(REG_DCXT),
-                              opnd_create_immed_int(VREG_OFFSET(DR_REG_VR0), OPSZ_12b)));
+            INSTR_CREATE_addi(
+                dcontext, opnd_create_reg(DR_REG_A1), opnd_create_reg(REG_DCXT),
+                opnd_create_immed_int(VREG_OFFSET(DR_REG_VR0) - CONTEXT_REBASE_OFFT,
+                                      OPSZ_12b)));
         /* For the following vector instructions, set the element width to 8b, and use 8
          * registers as a group (lmul=8).
          */
@@ -835,12 +836,13 @@ append_save_simd_reg(dcontext_t *dcontext, instrlist_t *ilist, bool absolute)
          *
          *           ma            ta         sew=8       lmul=8 */
         vtypei = (0b1 << 7) | (0b1 << 6) | (0b000 << 3) | 0b011;
-        memopnd = opnd_create_dcontext_field_via_reg_sz(
-            dcontext, DR_REG_A1, 0, reg_get_size_lmul(DR_REG_VR0, RV64_LMUL_8));
+        memopnd = opnd_create_base_disp(DR_REG_A1, REG_NULL, 0, 0,
+                                        reg_get_size_lmul(DR_REG_VR0, RV64_LMUL_8));
         APP(ilist,
-            INSTR_CREATE_addi(dcontext, opnd_create_reg(DR_REG_A1),
-                              opnd_create_reg(REG_DCXT),
-                              opnd_create_immed_int(VREG_OFFSET(DR_REG_VR0), OPSZ_12b)));
+            INSTR_CREATE_addi(
+                dcontext, opnd_create_reg(DR_REG_A1), opnd_create_reg(REG_DCXT),
+                opnd_create_immed_int(VREG_OFFSET(DR_REG_VR0) - CONTEXT_REBASE_OFFT,
+                                      OPSZ_12b)));
         /* For the following vector instructions, set the element width to 8b, and use 8
          * registers as a group (lmul=8).
          */

core/arch/riscv64/mangle.c

@@ -1,6 +1,6 @@
 /* **********************************************************
  * Copyright (c) 2022 Rivos, Inc.  All rights reserved.
- * Copyright (c) 2024 Foundation of Research and Technology, Hellas.
+ * Copyright (c) 2024-2025 Foundation of Research and Technology, Hellas.
  * **********************************************************/
 
 /*
@@ -219,7 +219,7 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci,
                                 opnd_create_reg(DR_REG_A0)));
     }
 
-    dstack_offs += 2 * XSP_SZ;
+    dstack_offs += XSP_SZ;
 
     /* Push vector registers. */
     if (proc_has_feature(FEATURE_VECTOR)) {
@@ -230,8 +230,8 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci,
          *
          *           ma            ta         sew=8       lmul=8 */
         vtypei = (0b1 << 7) | (0b1 << 6) | (0b000 << 3) | 0b011;
-        memopnd = opnd_create_dcontext_field_via_reg_sz(
-            dcontext, DR_REG_A0, 0, reg_get_size_lmul(DR_REG_VR0, RV64_LMUL_8));
+        memopnd = opnd_create_base_disp(DR_REG_A0, REG_NULL, 0, 0,
+                                        reg_get_size_lmul(DR_REG_VR0, RV64_LMUL_8));
         PRE(ilist, instr,
             INSTR_CREATE_addi(dcontext, opnd_create_reg(DR_REG_A0),
                               opnd_create_reg(DR_REG_SP),
@@ -301,8 +301,8 @@ insert_pop_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, instrlist
          *
          *           ma            ta         sew=8       lmul=8 */
         vtypei = (0b1 << 7) | (0b1 << 6) | (0b000 << 3) | 0b011;
-        memopnd = opnd_create_dcontext_field_via_reg_sz(
-            dcontext, DR_REG_A0, 0, reg_get_size_lmul(DR_REG_VR0, RV64_LMUL_8));
+        memopnd = opnd_create_base_disp(DR_REG_A0, REG_NULL, 0, 0,
+                                        reg_get_size_lmul(DR_REG_VR0, RV64_LMUL_8));
         PRE(ilist, instr,
             INSTR_CREATE_addi(dcontext, opnd_create_reg(DR_REG_A0),
                               opnd_create_reg(DR_REG_SP),

core/dispatch.c

@@ -1,6 +1,7 @@
 /* **********************************************************
  * Copyright (c) 2011-2023 Google, Inc.  All rights reserved.
  * Copyright (c) 2000-2010 VMware, Inc.  All rights reserved.
+ * Copyright (c) 2025 Foundation of Research and Technology, Hellas.
  * **********************************************************/
 
 /*
@@ -569,7 +570,17 @@ enter_fcache(dcontext_t *dcontext, fcache_enter_func_t entry, cache_pc pc)
      * paths were missed?
      */
     PTHREAD_JIT_READ();
+
+    /*
+     * XXX arithmetic with void pointers does not work on windows.
+     * Since RISCV is the only architecture that has CONTEXT_REBASE_OFFT != 0
+     * and it does not run windows, we can work around that with conditional compilation.
+     */
+#if (CONTEXT_REBASE_OFFT != 0)
+    (*entry)(((void *)dcontext) + CONTEXT_REBASE_OFFT);
+#else
     (*entry)(dcontext);
+#endif
     IF_WINDOWS(ASSERT_NOT_REACHED()); /* returns for signals on unix */
 }
 

core/ir/opnd_shared.c

@@ -1,6 +1,7 @@
 /* **********************************************************
  * Copyright (c) 2011-2022 Google, Inc.  All rights reserved.
  * Copyright (c) 2000-2010 VMware, Inc.  All rights reserved.
+ * Copyright (c) 2025 Foundation of Research and Technology, Hellas.
  * **********************************************************/
 
 /*
@@ -2905,7 +2906,8 @@ dcontext_opnd_common(dcontext_t *dcontext, bool absolute, reg_id_t basereg, int
             offs -= sizeof(unprotected_context_t);
         return opnd_create_base_disp(
             absolute ? REG_NULL : (basereg == REG_NULL ? REG_DCXT : basereg), REG_NULL, 0,
-            ((int)(ptr_int_t)(absolute ? dcontext : 0)) + offs, size);
+            ((int)(ptr_int_t)(absolute ? dcontext : 0)) + offs - CONTEXT_REBASE_OFFT,
+            size);
     }
 }
 
@@ -2950,7 +2952,7 @@ update_dcontext_address(opnd_t op, dcontext_t *old_dcontext, dcontext_t *new_dco
                       opnd_get_index(op) == REG_NULL,
                   "update_dcontext_address: invalid opnd");
     IF_X64(ASSERT_NOT_IMPLEMENTED(false));
-    offs = opnd_get_disp(op) - (uint)(ptr_uint_t)old_dcontext;
+    offs = opnd_get_disp(op) - (uint)(ptr_uint_t)old_dcontext + CONTEXT_REBASE_OFFT;
     if (offs >= 0 && offs < sizeof(dcontext_t)) {
         /* don't pass raw offset, add in upcontext size */
         offs += sizeof(unprotected_context_t);

core/unix/os.c

@@ -2,6 +2,7 @@
  * Copyright (c) 2010-2025 Google, Inc.  All rights reserved.
  * Copyright (c) 2011 Massachusetts Institute of Technology  All rights reserved.
  * Copyright (c) 2000-2010 VMware, Inc.  All rights reserved.
+ * Copyright (c) 2025 Foundation of Research and Technology, Hellas.
  * *******************************************************************************/
 
 /*
@@ -2378,6 +2379,9 @@ os_tls_init(void)
         if (last_thread_tls_exited) /* re-attach */
             last_thread_tls_exited = false;
     }
+#if (CONTEXT_REBASE_OFFT != 0)
+    set_thread_private_dcontext(NULL);
+#endif
     ASSERT(is_thread_tls_initialized());
 }
 
@@ -3134,7 +3138,7 @@ get_thread_private_dcontext(void)
                pid_cached != get_process_id());
     });
     READ_TLS_SLOT_IMM(TLS_DCONTEXT_OFFSET, dcontext);
-    return dcontext;
+    return (dcontext_t *)(((void *)dcontext) - CONTEXT_REBASE_OFFT);
 #else
     /* Assumption: no lock needed on a read => no race conditions between
      * reading and writing same tid!  Since both get and set are only for
@@ -3146,7 +3150,8 @@ get_thread_private_dcontext(void)
     if (tls_table != NULL) {
         for (i = 0; i < MAX_THREADS; i++) {
             if (tls_table[i].tid == tid) {
-                return tls_table[i].dcontext;
+                return (dcontext_t *)(((void *)tls_table[i].dcontext -
+                CONTEXT_REBASE_OFFT);
             }
         }
     }
@@ -3158,6 +3163,7 @@ get_thread_private_dcontext(void)
 void
 set_thread_private_dcontext(dcontext_t *dcontext)
 {
+    dcontext = (dcontext_t *)(((void *)dcontext) + CONTEXT_REBASE_OFFT);
 #ifdef HAVE_TLS
     ASSERT(is_thread_tls_allocated());
     WRITE_TLS_SLOT_IMM(TLS_DCONTEXT_OFFSET, dcontext);