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Ddr2 board update #48

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Ddr2 board update #48

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b7225c3
added 2 mig modes, added ddr3 interface to board, fixed clk_wiz probl…
ColdfireMC Apr 20, 2022
94b38e7
Adding board file. Basic Interface written. Still not enabled. WIP
ColdfireMC May 9, 2022
a43eb1a
new board
ColdfireMC Oct 1, 2022
a59c7fb
Merge branch 'Digilent:master' into master
ColdfireMC Dec 27, 2024
c53c163
added mig and vga interfaces for nexys4-ddr and nexys-a7
ColdfireMC Jan 8, 2025
3f5907e
Merge branch 'Digilent:master' into master
ColdfireMC Jan 8, 2025
3ba7e0a
Delete new/board_files/ads42xx/1.0 directory
ColdfireMC Jan 8, 2025
777d351
Delete new/board_files/stlv7325/1.0 directory
ColdfireMC Jan 8, 2025
0985718
Delete new/board_files/nexys_video/A.0/1.4 directory
ColdfireMC Jan 8, 2025
fdc7520
Update .gitignore
ColdfireMC Jan 8, 2025
81bc0c8
fixed missing vga interface
ColdfireMC Jan 9, 2025
ae554eb
Merge pull request #1 from ColdfireMC/master
ColdfireMC Jan 9, 2025
58ff3fe
fixed missing board component
ColdfireMC Jan 9, 2025
339f9a7
Merge pull request #2 from ColdfireMC/master
ColdfireMC Jan 9, 2025
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1 change: 1 addition & 0 deletions new/board_files/.gitignore
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1,462 changes: 1,462 additions & 0 deletions new/board_files/nexys-a7-100t/D.0/1.4/board.xml
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157 changes: 157 additions & 0 deletions new/board_files/nexys-a7-100t/D.0/1.4/mig.prj
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project NoOfControllers="1">



<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->

<ModuleName>design_1_mig_7series_0_0</ModuleName>

<dci_inouts_inputs>1</dci_inouts_inputs>

<dci_inputs>1</dci_inputs>

<Debug_En>OFF</Debug_En>

<DataDepth_En>1024</DataDepth_En>

<LowPower_En>ON</LowPower_En>

<XADC_En>Enabled</XADC_En>

<TargetFPGA>xc7a100t-csg324/-1</TargetFPGA>

<Version>4.2</Version>

<SystemClock>Single-Ended</SystemClock>

<ReferenceClock>No Buffer</ReferenceClock>

<SysResetPolarity>ACTIVE LOW</SysResetPolarity>

<BankSelectionFlag>FALSE</BankSelectionFlag>

<InternalVref>1</InternalVref>

<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>

<dci_cascade>0</dci_cascade>

<FPGADevice>
<selected>7a/xc7a50t-csg324</selected>
</FPGADevice>

<Controller number="0">
<MemoryDevice>DDR2_SDRAM/Components/MT47H64M16HR-25E</MemoryDevice>
<TimePeriod>3077</TimePeriod>
<VccAuxIO>1.8V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
<InputClkFreq>99.997</InputClkFreq>
<UIExtraClocks>1</UIExtraClocks>
<MMCM_VCO>1200</MMCM_VCO>
<MMCMClkOut0> 6.000</MMCMClkOut0>
<MMCMClkOut1>1</MMCMClkOut1>
<MMCMClkOut2>1</MMCMClkOut2>
<MMCMClkOut3>1</MMCMClkOut3>
<MMCMClkOut4>1</MMCMClkOut4>
<DataWidth>16</DataWidth>
<DeepMemory>1</DeepMemory>
<DataMask>1</DataMask>
<ECC>Disabled</ECC>
<Ordering>Strict</Ordering>
<BankMachineCnt>4</BankMachineCnt>
<CustomPart>FALSE</CustomPart>
<NewPartName/>
<RowAddress>13</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<C0_MEM_SIZE>134217728</C0_MEM_SIZE>
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
<PinSelection>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="M4" SLEW="" VCCAUX_IO="" name="ddr2_addr[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="R2" SLEW="" VCCAUX_IO="" name="ddr2_addr[10]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="K5" SLEW="" VCCAUX_IO="" name="ddr2_addr[11]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="N6" SLEW="" VCCAUX_IO="" name="ddr2_addr[12]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="P4" SLEW="" VCCAUX_IO="" name="ddr2_addr[1]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="M6" SLEW="" VCCAUX_IO="" name="ddr2_addr[2]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="T1" SLEW="" VCCAUX_IO="" name="ddr2_addr[3]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="L3" SLEW="" VCCAUX_IO="" name="ddr2_addr[4]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="P5" SLEW="" VCCAUX_IO="" name="ddr2_addr[5]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="M2" SLEW="" VCCAUX_IO="" name="ddr2_addr[6]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="N1" SLEW="" VCCAUX_IO="" name="ddr2_addr[7]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="L4" SLEW="" VCCAUX_IO="" name="ddr2_addr[8]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="N5" SLEW="" VCCAUX_IO="" name="ddr2_addr[9]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="P2" SLEW="" VCCAUX_IO="" name="ddr2_ba[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="P3" SLEW="" VCCAUX_IO="" name="ddr2_ba[1]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="R1" SLEW="" VCCAUX_IO="" name="ddr2_ba[2]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="L1" SLEW="" VCCAUX_IO="" name="ddr2_cas_n"/>
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL18_II" PADName="L5" SLEW="" VCCAUX_IO="" name="ddr2_ck_n[0]"/>
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL18_II" PADName="L6" SLEW="" VCCAUX_IO="" name="ddr2_ck_p[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="M1" SLEW="" VCCAUX_IO="" name="ddr2_cke[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="K6" SLEW="" VCCAUX_IO="" name="ddr2_cs_n[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="T6" SLEW="" VCCAUX_IO="" name="ddr2_dm[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="U1" SLEW="" VCCAUX_IO="" name="ddr2_dm[1]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="R7" SLEW="" VCCAUX_IO="" name="ddr2_dq[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="V5" SLEW="" VCCAUX_IO="" name="ddr2_dq[10]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="U4" SLEW="" VCCAUX_IO="" name="ddr2_dq[11]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="V4" SLEW="" VCCAUX_IO="" name="ddr2_dq[12]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="T4" SLEW="" VCCAUX_IO="" name="ddr2_dq[13]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="V1" SLEW="" VCCAUX_IO="" name="ddr2_dq[14]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="T3" SLEW="" VCCAUX_IO="" name="ddr2_dq[15]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="V6" SLEW="" VCCAUX_IO="" name="ddr2_dq[1]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="R8" SLEW="" VCCAUX_IO="" name="ddr2_dq[2]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="U7" SLEW="" VCCAUX_IO="" name="ddr2_dq[3]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="V7" SLEW="" VCCAUX_IO="" name="ddr2_dq[4]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="R6" SLEW="" VCCAUX_IO="" name="ddr2_dq[5]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="U6" SLEW="" VCCAUX_IO="" name="ddr2_dq[6]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="R5" SLEW="" VCCAUX_IO="" name="ddr2_dq[7]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="T5" SLEW="" VCCAUX_IO="" name="ddr2_dq[8]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="U3" SLEW="" VCCAUX_IO="" name="ddr2_dq[9]"/>
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL18_II" PADName="V9" SLEW="" VCCAUX_IO="" name="ddr2_dqs_n[0]"/>
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL18_II" PADName="V2" SLEW="" VCCAUX_IO="" name="ddr2_dqs_n[1]"/>
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL18_II" PADName="U9" SLEW="" VCCAUX_IO="" name="ddr2_dqs_p[0]"/>
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL18_II" PADName="U2" SLEW="" VCCAUX_IO="" name="ddr2_dqs_p[1]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="M3" SLEW="" VCCAUX_IO="" name="ddr2_odt[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="N4" SLEW="" VCCAUX_IO="" name="ddr2_ras_n"/>
<Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="N2" SLEW="" VCCAUX_IO="" name="ddr2_we_n"/>
</PinSelection>
<System_Clock>
<Pin Bank="35" PADName="E3(MRCC_P)" name="sys_clk_i"/>
</System_Clock>
<System_Control>
<Pin Bank="Select Bank" PADName="No connect" name="sys_rst"/>
<Pin Bank="Select Bank" PADName="No connect" name="init_calib_complete"/>
<Pin Bank="Select Bank" PADName="No connect" name="tg_compare_error"/>
</System_Control>
<TimingParameters>
<Parameters tfaw="45" tras="40" trcd="15" trefi="7.8" trfc="127.5" trp="12.5" trrd="10" trtp="7.5" twtr="7.5"/>
</TimingParameters>
<mrBurstLength name="Burst Length">8</mrBurstLength>
<mrBurstType name="Burst Type">Sequential</mrBurstType>
<mrCasLatency name="CAS Latency">5</mrCasLatency>
<mrMode name="Mode">Normal</mrMode>
<mrDllReset name="DLL Reset">No</mrDllReset>
<mrPdMode name="PD Mode">Fast exit</mrPdMode>
<mrWriteRecovery name="Write Recovery">5</mrWriteRecovery>
<emrDllEnable name="DLL Enable">Enable-Normal</emrDllEnable>
<emrOutputDriveStrength name="Output Drive Strength">Fullstrength</emrOutputDriveStrength>
<emrCSSelection name="Controller Chip Select Pin">Enable</emrCSSelection>
<emrCKSelection name="Memory Clock Selection">1</emrCKSelection>
<emrRTT name="RTT (nominal) - ODT">50ohms</emrRTT>
<emrPosted name="Additive Latency (AL)">0</emrPosted>
<emrOCD name="OCD Operation">OCD Exit</emrOCD>
<emrDQS name="DQS# Enable">Enable</emrDQS>
<emrRDQS name="RDQS Enable">Disable</emrRDQS>
<emrOutputs name="Outputs">Enable</emrOutputs>
<PortInterface>AXI</PortInterface>
<AXIParameters>
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
<C0_S_AXI_ADDR_WIDTH>27</C0_S_AXI_ADDR_WIDTH>
<C0_S_AXI_DATA_WIDTH>128</C0_S_AXI_DATA_WIDTH>
<C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
</AXIParameters>
</Controller>


</Project>
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