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Merge pull request #124 from DUNE-DAQ/feature/timing_source_mux
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Feature/timing source mux
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@strilov
strilov authored Dec 9, 2024
2 parents 7f57ea5 + 22b99be commit a6081b1
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Showing 70 changed files with 1,454 additions and 577 deletions.
12 changes: 12 additions & 0 deletions config/etc/addrtab/v7xx/fanout_fib_v2/ipbus_freq_ctr.xml
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<?xml version="1.0" encoding="ISO-8859-1"?>

<node description="Frequency counter" fwinfo="endpoint;width=1">
<node id="ctrl" address="0x0">
<node id="chan_sel" mask="0xf"/>
<node id="en_crap_mode" mask="0x10"/>
</node>
<node id="freq" address="0x1">
<node id="count" mask="0xffffff"/>
<node id="valid" mask="0x1000000"/>
</node>
</node>
9 changes: 9 additions & 0 deletions config/etc/addrtab/v7xx/fanout_fib_v2/opencores_i2c.xml
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<?xml version="1.0" encoding="ISO-8859-1"?>

<node description="I2C master controller" fwinfo="endpoint;width=3">
<node id="ps_lo" address="0x0" description="Prescale low byte"/>
<node id="ps_hi" address="0x1" description="Prescale low byte"/>
<node id="ctrl" address="0x2" description="Control"/>
<node id="data" address="0x3" description="Data"/>
<node id="cmd_stat" address="0x4" description="Command / status"/>
</node>
26 changes: 26 additions & 0 deletions config/etc/addrtab/v7xx/fanout_fib_v2/pdts_ep_mon.xml
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<node id="ep_core" description="PDTS endpoint core wrapper" fwinfo="endpoint" class="EndpointNode">
<node id="csr" address="0x0" fwinfo="endpoint;width=1">
<node id="ctrl" address="0x0">
<node id="ep_en" mask="0x1"/>
<node id="ctr_rst" mask="0x2"/>
<node id="addr" mask="0xffff0000"/>
</node>
<node id="stat" address="0x1">
<node id="ep_stat" mask="0x0f"/>
<node id="ep_rdy" mask="0x10"/>
<node id="ep_txen" mask="0x20"/>
<node id="ctrs_rdy" mask="0x40"/>
</node>
</node>
<node id="tstamp" address="0x2" mode="block" size="0x2" fwinfo="endpoint;width=1"/>
<node id="cmd_ctrs" address="0x4" fwinfo="endpoint;width=1">
<node id="addr" address="0x0"/>
<node id="data" address="0x1" size="0x100" mode="port"/>
</node>
<node id="cmd_log" address="0x8" fwinfo="endpoint;width=2">
<node id="tstamp_l" address="0x0"/>
<node id="tstamp_h" address="0x1"/>
<node id="cmd" address="0x2"/>
</node>
<node id="dcmd_ctrs" address="0x10" mode="block" size="0x8" fwinfo="endpoint;width=3"/>
</node>
39 changes: 39 additions & 0 deletions config/etc/addrtab/v7xx/fanout_fib_v2/pdts_fib_v2_io.xml
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<node id="io" description="FIB V2 IO" fwinfo="endpoint" class="FIBV2IONode">
<node id="csr" address="0x0" description="ctrl/stat register" fwinfo="endpoint;width=1">
<node id="ctrl" address="0x0">
<node id="soft_rst" mask="0x1"/>
<node id="nuke" mask="0x2"/>
<node id="rst" mask="0x4"/>
<node id="clk_select" mask="0x8"/>
<node id="clk_enable" mask="0x10"/>
<node id="sfp_tx_disable" mask="0xff00"/>
<node id="bp_tx_edge" mask="0x10000"/>
<node id="sfp_tx_edge" mask="0x20000"/>
</node>
<node id="stat" address="0x1">
<node id="mmcm_ok" mask="0x1"/>
<node id="pll_ok" mask="0x2"/>
<node id="mmcm_sticky" mask="0x4"/>
<node id="pll_sticky" mask="0x8"/>
<node id="sfp_los" mask="0xff00"/>
<node id="sfp_fault" mask="0xff0000"/>
</node>
</node>
<node id="config" address="0x2" description="board/firmware config" fwinfo="endpoint;width=1">
<node id="no_cdr" mask="0xff000000"/>
<node id="board_type" mask="0xff0000"/>
<node id="carrier_type" mask="0xff00"/>
<node id="design_type" mask="0xff"/>
<node id="clock_frequency" address="0x1" mask="0xffffffff"/>
</node>
<node id="i2c" address="0x08" module="file://opencores_i2c.xml" class="I2CMasterNode" parameters="UID_PROM=0x50;SI5345=0x68;Expander1=0x74;Expander2=0x75;AX3_Switch=0x21"/>
<node id="i2c_sfp0" address="0x10" module="file://opencores_i2c.xml" class="I2CMasterNode" parameters="SFP_EEProm=0x50;SFP_Diag=0x51"/>
<node id="i2c_sfp1" address="0x18" module="file://opencores_i2c.xml" class="I2CMasterNode" parameters="SFP_EEProm=0x50;SFP_Diag=0x51"/>
<node id="i2c_sfp2" address="0x20" module="file://opencores_i2c.xml" class="I2CMasterNode" parameters="SFP_EEProm=0x50;SFP_Diag=0x51"/>
<node id="i2c_sfp3" address="0x28" module="file://opencores_i2c.xml" class="I2CMasterNode" parameters="SFP_EEProm=0x50;SFP_Diag=0x51"/>
<node id="i2c_sfp4" address="0x30" module="file://opencores_i2c.xml" class="I2CMasterNode" parameters="SFP_EEProm=0x50;SFP_Diag=0x51"/>
<node id="i2c_sfp5" address="0x38" module="file://opencores_i2c.xml" class="I2CMasterNode" parameters="SFP_EEProm=0x50;SFP_Diag=0x51"/>
<node id="i2c_sfp6" address="0x40" module="file://opencores_i2c.xml" class="I2CMasterNode" parameters="SFP_EEProm=0x50;SFP_Diag=0x51"/>
<node id="i2c_sfp7" address="0x48" module="file://opencores_i2c.xml" class="I2CMasterNode" parameters="SFP_EEProm=0x50;SFP_Diag=0x51"/>
<node id="freq" address="0x50" module="file://ipbus_freq_ctr.xml" class="FrequencyCounterNode"/>
</node>
12 changes: 12 additions & 0 deletions config/etc/addrtab/v7xx/fanout_fib_v2/pdts_upstream_cdr.xml
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<node id="upstream_cdr" description="CDR block for upstream rx" fwinfo="endpoint;width=1" class="UpstreamCDRNode">
<node id="ctrl" address="0x0">
<node id="resync" mask="0x1"/>
</node>
<node id="stat" address="0x1">
<node id="locked" mask="0x1"/>
<node id="los" mask="0x2"/>
<node id="phase" mask="0x70"/>
<node id="err" mask="0x80"/>
<node id="valid" mask="0xff00"/>
</node>
</node>
7 changes: 7 additions & 0 deletions config/etc/addrtab/v7xx/fanout_fib_v2/pdts_upstream_mux.xml
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<node id="pdts_upstream_mux" description="Switch between different downstream timing sources and pass upstream" fwinfo="endpoint">
<node id="csr" address="0x0" fwinfo="endpoint;width=0">
<node id="ctrl" address="0x0">
<node id="src" mask="0x7"/>
</node>
</node>
</node>
13 changes: 13 additions & 0 deletions config/etc/addrtab/v7xx/fanout_fib_v2/top_fib_v2.xml
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<node id="TOP" class="FanoutDesign">
<node id="io" address="0x0" module="file://pdts_fib_v2_io.xml"/>
<node id="endpoint0" address="0x100" module="file://pdts_ep_mon.xml"/>
<node id="us_mux" address="0x400" module="file://pdts_upstream_mux.xml"/>
<node id="cdr0" address="0x0600" module="file://pdts_upstream_cdr.xml"/>
<node id="cdr1" address="0x0800" module="file://pdts_upstream_cdr.xml"/>
<node id="cdr2" address="0x0A00" module="file://pdts_upstream_cdr.xml"/>
<node id="cdr3" address="0x0C00" module="file://pdts_upstream_cdr.xml"/>
<node id="cdr4" address="0x0E00" module="file://pdts_upstream_cdr.xml"/>
<node id="cdr5" address="0x1000" module="file://pdts_upstream_cdr.xml"/>
<node id="cdr6" address="0x1200" module="file://pdts_upstream_cdr.xml"/>
<node id="cdr7" address="0x1400" module="file://pdts_upstream_cdr.xml"/>
</node>
7 changes: 4 additions & 3 deletions config/etc/addrtab/v7xx/kerberos_mib_v2/pdts_mib_v2_io.xml
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Expand Up @@ -15,9 +15,10 @@
<node id="sfp0_los" mask="0x8"/>
<node id="sfp1_los" mask="0x10"/>
<node id="sfp2_los" mask="0x20"/>
<node id="pll_lol" mask="0x40"/>
<node id="mmcm_ok" mask="0x80"/>
<node id="mmcm_sticky" mask="0x100"/>
<node id="pll_ok" mask="0x40"/>
<node id="pll_sticky" mask="0x80"/>
<node id="mmcm_ok" mask="0x100"/>
<node id="mmcm_sticky" mask="0x200"/>
</node>
</node>
<node id="config" address="0x2" description="board/firmware config" fwinfo="endpoint;width=1">
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2 changes: 1 addition & 1 deletion config/etc/addrtab/v7xx/kerberos_mib_v2/pdts_timing_source_mux.xml
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<node id="pdts_timing_source_mux" description="Switch between upstream timing sources" fwinfo="endpoint">
<node id="csr" address="0x0" fwinfo="endpoint;width=0">
<node id="ctrl" address="0x0">
<node id="src" mask="0x1"/>
<node id="src" mask="0x3"/>
</node>
</node>
</node>
2 changes: 1 addition & 1 deletion include/timing/BoreasDesign.hpp
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Expand Up @@ -47,7 +47,7 @@ class BoreasDesign : public MasterDesign, public HSIDesignInterface
* @brief Prepare the timing master for data taking.
*
*/
void configure() const override;
void configure(ClockSource clock_source, TimestampSource ts_source) const override;

/**
* @brief Give info to collector.
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54 changes: 54 additions & 0 deletions include/timing/CDCLVD110Node.hpp
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/**
* @file CDCLVD110Node.hpp
*
* CDCLVD110Node is a class providing an interface
* to the physical CDCLVD110 IC.
*
* This is part of the DUNE DAQ Software Suite, copyright 2020.
* Licensing/copyright details are in the COPYING file that you should have
* received with this code.
*/

#ifndef TIMING_INCLUDE_TIMING_CDCLVD110NODE_HPP_
#define TIMING_INCLUDE_TIMING_CDCLVD110NODE_HPP_

#include "timing/ClockGeneratorInterface.hpp"

#include "timing/timinghardwareinfo/Structs.hpp"
#include "timing/timinghardwareinfo/Nljs.hpp"

#include "ers/Issue.hpp"

#include <string>

namespace dunedaq {
namespace timing {

/**
* @class CDCLVD110Node
*
* @brief uhal::Node implementing CDCLVD110 interface
*/
class CDCLVD110Node
: public ClockGeneratorInterface
{
UHAL_DERIVEDNODE(CDCLVD110Node)
public:
explicit CDCLVD110Node(const uhal::Node& node);
virtual ~CDCLVD110Node();

/**
* @brief Get status string, optionally print.
*/
std::string get_status(bool print_out = false) const override;

/**
* @brief Get status string, optionally print.
*/
void get_info(timinghardwareinfo::TimingPLLMonitorData& mon_data) const override;
};

} // namespace timing
} // namespace dunedaq

#endif // TIMING_INCLUDE_TIMING_CDCLVD110NODE_HPP_
73 changes: 0 additions & 73 deletions include/timing/CRTDesign.hpp
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55 changes: 0 additions & 55 deletions include/timing/CRTDesignInterface.hpp
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