From f046b4c934a9a1fd577980131b0df963634f51eb Mon Sep 17 00:00:00 2001
From: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Date: Mon, 14 Oct 2024 13:52:33 +0700
Subject: [PATCH] boards: s32z270: enable support psi5

enable support psi5

Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
---
 boards/nxp/s32z2xxdc2/doc/index.rst |  2 +
 dts/arm/nxp/nxp_s32z27x_r52.dtsi    | 73 ++++++++++++++++++++++++++++-
 2 files changed, 74 insertions(+), 1 deletion(-)

diff --git a/boards/nxp/s32z2xxdc2/doc/index.rst b/boards/nxp/s32z2xxdc2/doc/index.rst
index 9cb0972bf8fc7e..16118d0028f6d4 100644
--- a/boards/nxp/s32z2xxdc2/doc/index.rst
+++ b/boards/nxp/s32z2xxdc2/doc/index.rst
@@ -60,6 +60,8 @@ The boards support the following hardware features:
 +-----------+------------+-------------------------------------+
 | DSPI      | on-chip    | spi                                 |
 +-----------+------------+-------------------------------------+
+| PSI5      | on-chip    | psi5                                |
++-----------+------------+-------------------------------------+
 
 Other hardware features are not currently supported by the port.
 
diff --git a/dts/arm/nxp/nxp_s32z27x_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_r52.dtsi
index 013c80c87eadaa..99ff6bdee2ac0d 100644
--- a/dts/arm/nxp/nxp_s32z27x_r52.dtsi
+++ b/dts/arm/nxp/nxp_s32z27x_r52.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright 2022-2024 NXP
+ * Copyright 2022-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -1259,5 +1259,76 @@
 			status = "disabled";
 		};
 
+		psi5_0: psi5@401e0000 {
+			compatible = "nxp,s32-psi5";
+			reg = <0x401e0000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			psi5_0_ch0: ch@0 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <0>;
+				interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+
+			psi5_0_ch1: ch@1 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <1>;
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+
+			psi5_0_ch2: ch@2 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <2>;
+				interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+
+			psi5_0_ch3: ch@3 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <3>;
+				interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+		};
+
+		psi5_1: psi5@421e0000 {
+			compatible = "nxp,s32-psi5";
+			reg = <0x421e0000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			psi5_1_ch0: ch@0 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <0>;
+				interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+
+			psi5_1_ch1: ch@1 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <1>;
+				interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+
+			psi5_1_ch2: ch@2 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <2>;
+				interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+
+			psi5_1_ch3: ch@3 {
+				compatible = "nxp,s32-psi5-channel";
+				reg = <3>;
+				interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				status = "disabled";
+			};
+		};
 	};
 };