SH2 on the 32X
The ABI for SuperH is to pass the first four parameters in r4 to r7, and any others on the stack. Registers r8 to r14 and pr MUST be preserved if you use them, normally by pushing them on the stack, which is r15. r0 to r7 may be freely changed without saving, and the result is returned in r0 as long as it's 4 bytes or less. For 8 bytes or less, the result is returned in r0 and r1.
Toshiyasu Morita, Programming the 32x FAQ
The early revisions of the 32x use the 2.5 cut of the SH2, which has a problem with interrupts. Specifically, if a low priority interrupt occurs, and within a 3-cycle window a higher priority interrupt occurs, then the 2.5 revision of the SH2 will jump to the low priority interrupt vector and lose the high priority interrupt. The SR will still be set to the number of the higher priority interrupt, however.
The first half of the unified interrupt handler is to vector all the interrupts to a common routine, which checks the SR for the proper proper interrupt to handle. In this way, the higher priority interrupt is serviced first, which is the correct behavior.
The second component of the unified interrupt handler is the free-running timer's output is tied to the least significant bit of the interrupt request lines, which toggles the least significant bit of the interrupt request lines. If the interrupt request level is nonzero this will cause it to bounce between odd/even which effectively "retriggers" the interrupt, so the low-priority interrupt will be serviced.
To mask interrupts on the 32x you must put a "2" into the SR - putting a zero will allow the free-running timer to trigger interrupts, since it toggles the least significant bit of the interrupt request lines, which causes it to generate interrupt 0 and interrupt 1 requests continuously which will cause a degradation of CPU performance.
In the schematics, FTOA (FRTimer Output A) is connected directly to /IRL0 (on both CPUs). The FRT int is disabled, but the FRT is running with it set to set or clear the timer compare output when compare register A matches the FRT counter. The register is set to 1. It is also set to clear the FRT counter when the compare is equal. So the FRT is always running - counting up to 1, then setting/clearing FTOA, and clearing the counter, then counting up to 1 again.
The interrupt code toggles the bit in the FRT that tells it to set or clear FTOA. So FTOA is toggled hi/low every 1 count - and the FRT clock is set to Fs/8. So every 16 clock cycles, FTOA will toggle on/off once. This will change /IRL0 every 16 clock cycles. This is why every interrupt uses two levels - one is the real interrupt level, and the other is to allow FTOA to bump the int 16 clock cycles later.
So no FRT int occurs, but rather an IRL int occurs, then 16 clock cycles later, and IRL+1 int occurs... and continues to occur every 16 cycles until the system processes the IRL int that originally occured. You need to keep the int mask high enough to ignore level 1 ints or the cpu will get interrupted every 16 clock cycles by the FRT bump.
Initialization of the free run timer must be done whether or not interrupt is used in coping with SH2 interrupt.
Free running timer initialization - [1994-09-23]
When two or more types of interrupts are used by the SH2, an interrupt of the same level may be acknowledged twice consecutively in relation to the occurrence of a single interrupt.
When the CMD INT occurs, the SH2 acknowledges the interrupt (recognized as level 8) and starts to process it. However, if a V-INT occurs before the SR is masked, the SH2 processes the V-INT instead since it has higher priority than the currently masked level (in this case, 8). Moreover, the FRT is set and the V-INT is cleared during this process, changing the external interrupt level as a result.
After the V-INT is processed, processing on the previously acknowledged CMD INT begins again. However, if the FRT output value changes before the SR is masked, the SH2 will judge that a higher priority level interrupt has occurred than the currently masked level (in this case level 8). As a result, the SH2 begins to process a CMD INT (acknowledged as level 9) instead. After this CMD INT is processed, the SH2 will process the CMD INT acknowledged as a level 8 interrupt once again. This means that processing on the CMD INT will occur twice, even though it actually occurred once. Refer to the interrupt handler in the bulletin (This code can also be found in the 32X Hardware Manual Supplement 2).
(Note: this problem only occurs on the 32X. It does not occur on the Saturn.)
32X Technical Bulletin #27 - SH2 Interrupt Problems on the 32X - [1994-12-08]